Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-03-07
2006-03-07
Lamarre, Guy (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C365S185220, C365S200000, C365S201000, C714S030000
Reexamination Certificate
active
07010736
ABSTRACT:
An address sequencer is fabricated on a semiconductor substrate having flash memory cells fabricated thereon for sequencing through the flash memory cells during BIST (built-in-self-test) of the flash memory cells. The address sequencer includes an address sequencer control logic and address sequencer buffers fabricated on the semiconductor substrate. The address sequencer buffers generate a plurality of bits indicating an address of the flash memory cells. The address sequencer control logic controls the buffers to sequence through a respective sequence of bit patterns for each of a plurality of BIST modes.
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Bautista, Jr. Edward V.
Bill Colin
Cheah Ken Cheong
Hamilton Darlene G.
Kucera Joseph
Advanced Micro Devices , Inc.
Alphonse Fritz
Choi Monica H.
Lamarre Guy
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