Address sequencer within BIST (Built-in-Self-Test) system

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Details

C365S185220, C365S200000, C365S201000, C714S030000

Reexamination Certificate

active

07010736

ABSTRACT:
An address sequencer is fabricated on a semiconductor substrate having flash memory cells fabricated thereon for sequencing through the flash memory cells during BIST (built-in-self-test) of the flash memory cells. The address sequencer includes an address sequencer control logic and address sequencer buffers fabricated on the semiconductor substrate. The address sequencer buffers generate a plurality of bits indicating an address of the flash memory cells. The address sequencer control logic controls the buffers to sequence through a respective sequence of bit patterns for each of a plurality of BIST modes.

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patent: 6415403 (2002-07-01), Huang et al.
patent: 6543016 (2003-04-01), Lewandowski et al.
patent: 6760865 (2004-07-01), Ledford et al.

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