Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1998-06-05
2001-02-06
De Cady, Albert (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S735000
Reexamination Certificate
active
06185714
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an address trap comparator used in a computer system.
2. Description of the Related Art
Generally, in a computer system, a plurality of address trap comparators are provided, and the address trap comparators are controlled by a central processing unit (CPU). That is, when an address trap occurs in one of the address trap comparators, the CPU carries out an interrupt operation or the like in accordance with the address trap signal of the one of the address trap comparators.
A prior art address trap comparator is constructed by an address trap register for storing a reference address, a bit-by-bit comparator for comparing an address with the reference address stored in the address trap register on the bit-by-bit basis, and an all-bit comparator for detecting whether or not the outputs of the bit-by-bit comparator are the same. This will be explained later in detail.
In the above-mentioned prior art address trap comparator, a test mode is carried out to detect a fault such as a “stuck-at-1” fault or a “stuck-at-0” fault. Note that a “stuck-at-1” fault and a “stuck-at-0” fault will be explained later. For this purpose, special test patterns are supplied to the address trap comparator. This requires a large number of clock signal pulses, which increase the test time.
SUMMARY OF THE INVENTION
It is an object of the present invention to reduce the test time for detecting “stuck-at-1” and “stuck-at-0” faults in an address trap comparator.
According to the present invention, in an N-bit address trap comparator, an N-bit address trap register stores an N-bit reference address, a bit-by-bit comparator compares an N-bit address with the N-bit reference address bit-by-bit, and an all-bit comparator detects whether or not all outputs of the bit-by-bit comparator have the same value. In a test mode, the N-bit reference address is reset so that a first bit of the N-bit reference address is caused to be a first binary value and the other bits are caused to be a second binary value. Also, the second binary value is set in all bits of the N-bit address, and then, the N-bit reference address is shifted within the N-bit address trap register.
Thus, a test mode for “stuck-at-1” and “stuck-at-0” faults can be carried out without special test patterns.
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Cady Albert De
Foley & Lardner
NEC Corporation
Ton David
LandOfFree
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