Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2007-06-07
2010-11-09
Torres, Joseph D (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S795000
Reexamination Certificate
active
07831894
ABSTRACT:
Address generation for contention-free memory mappings of turbo codes with ARP (almost regular permutation) interleaves. A novel means is presented by which anticipatory address generation is employed using an index functionthat is based on an address mappingwhich corresponds to an interleave inverse order of decoding processing (π−1). In accordance with parallel turbo decoding processing, instead of performing the natural order phase decoding processing by accessing data elements from memory bank locations sequentially, the accessing of addresses is performed based on the index functionthat is based on an mapping and the interleave (π) employed within the turbo coding. In other words, the accessing data elements from memory bank locations is not sequential for natural order phase decoding processing. The index functionalso allows for the interleave (π) order phase decoding processing to be performed by accessing data elements from memory bank locations sequentially.
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Lee Tak K.
Shen Ba-Zhong
Broadcom Corporation
Garlick & Harrison & Markison
Short Shayne X.
Torres Joseph D
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