Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2005-10-18
2005-10-18
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C711S200000
Reexamination Certificate
active
06957373
ABSTRACT:
An address generator is provided for generating addresses for testing an addressable circuit. The address generator can include a base address register for buffer-storing a base address. The base address register can be assigned an associated offset register group having a plurality of offset registers for buffer-storing relative address values. Further, the address generator can include a first multiplexer circuit which is dependent on a base register selection control signal, switches through an address buffer-stored in the base address register to a first input of an addition circuit and to an address bus, which is connected to the circuit to be tested. A second multiplexer circuit can be dependent on the base register selection control signal, through-connects the offset register group associated with the through-connected base address register to a third multiplexer circuit, which is dependent on an offset register selection control signal.
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patent: 4779084 (1988-10-01), Tanaka et al.
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patent: 5883905 (1999-03-01), Eastburn
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Ernst Wolfgang
Krause Gunnar
Kuhn Justus
Luepke Jens
Mueller Jochen
De'cady Albert
Infineon - Technologies AG
Jenkins & Wilson & Taylor, P.A.
Tabone, Jr. John J.
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