Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2000-03-08
2002-10-29
Chung, Phung M. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C365S200000, C714S710000
Reexamination Certificate
active
06473872
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an address decoding system and method for decoding an address signal to address components in a memory bank, and more particularly to an address decoding system and method for separately addressing a pair of defective components in a memory bank to replace the defective components with redundant components.
BACKGROUND OF THE INVENTION
Generally, dynamic random access memories (DRAMs) are organized in a bank structure of two-dimensional cells in rows and columns. Memory cells may be accessed via wordlines and bit lines. The wordlines are driven from row paths, and the bit lines run across a memory bank. Each cross point realizes an access to cell information of each cell connected to a selected wordline.
To achieve a high yield efficiency, each memory bank is provided with a redundancy block having redundant wordlines for replacement of defective wordlines in the memory bank. Each redundancy block associated with each memory bank also has an independent sense amplifier system.
FIG. 1
illustrates a common structure of a DRAM bank
10
including a redundancy block
11
. The advantage of using a redundancy block
11
is to make it possible to repair defective wordlines in a memory bank
10
on which failures have occurred during or prior to testing a memory chip. All redundant wordlines may be concentrated in a redundancy block
11
next to memory blocks
12
. In such configuration, it is possible to control the redundancy block
11
and the memory blocks
12
independently. Referring to
FIG. 1
, a conventional row address decoder
14
receives an n-bit row address signal ADD<n> for addressing wordlines in a memory bank
10
. The row address signal ADD<n> can also address the redundant wordlines in the redundancy block
11
.
Since DRAM is usually configured to a shared row address decoding architecture, a pair of wordlines WLm and WLn in the memory bank
10
are addressed by the row address signal ADD<n>. The pair of wordlines are typically addressed together at the same time. In other words, the pair of wordlines WLm and WLn cannot be addressed separately with the row address signal ADD<n> decoded by the row address decoder
14
. Thus, if there are failures on both the wordlines WLm and WLn in the memory bank
10
, the defective wordlines WLm and WLn cannot be replaced with two redundant wordlines in the redundancy block
11
because sense amplifiers associated with the redundancy block
11
can only support data sensing of a single wordline at a time. As a result, the memory bank
10
becomes unrepairable.
FIG. 2
shows a more detailed illustration of addressing wordlines with the n-bit row address signal ADD<n>. For example, in a memory chip with the size of 64M or more, a row address decoder requires a two-dimensional scheme. That is, the row address decoder
14
has an X-decoder
16
and a Y-decoder
18
for outputting an X-signal X<m> and a Y-signal Y<n-m>, respectively, by decoding the row address signal ADD<n>. It is assumed that the n-bit row address signal ADD<n> consists of m-bit X-data corresponding to the X-signal X<m> and (n-m)-bit Y-data corresponding to the Y-signal Y<n-m>. Each wordline in memory bank can be addressed with a combination of the X-signal X<m> and the Y-signal Y<n-m>. Thus, if one of a pair of wordlines in a memory bank, addressed by a row address signal, is defective, the row address decoder
14
decodes the row address signal to select the defective one of the pair of wordlines so that the defective wordline can be replaced with a redundant wordline addressed by the row address signal.
However, if failures occur on both the pair of wordlines that are addressed by the row address signal at the same time, the two defective wordlines cannot be replaced with two different redundant wordlines because the redundancy block structure allows only one selected redundant wordline at a time. That is, only one of the pair of defective wordlines can be replaced with one redundant wordline at a time. Thus, in a conventional row address decoding system, a memory bank becomes unrepairable if a pair of wordlines sharing a row address in the bank are defective.
Therefore, a need exists for an address decoding system that can decode a row address signal shared by a pair of wordlines in a memory bank to address the pair of wordlines separately, so that if the pair of wordlines are defective, each defective wordline can be separately selected and replaced with different redundant wordlines in a redundancy block.
SUMMARY OF THE INVENTION
The present invention provides an address decoding system and method for tolerating failures on wordlines in a memory bank that are addressed by a common row address signal. The system of the present invention includes a first decoder for decoding the row address signal to generate a first signal addressing wordlines in a first half of the memory bank, and a second decoder for decoding the row address signal with fuse data corresponding to status of fuses associated with wordlines in the memory bank to generate a second signal addressing wordlines in a second half of the memory bank, wherein the first and second signals respectively select first and second wordlines at the same time, and the first and second wordlines are in the first half and the second half of the memory bank, respectively. The system also includes a redundancy block associated with the memory bank, for storing redundant wordlines to be replaced with defective wordlines in the memory bank, wherein one of the redundant wordlines is addressed by the row address signal and replaced with one of the defective wordlines, and the defective wordline is addressed by one of the first and second signals. When the row address signal has m-bit X-data and (n-m)-bit Y-data, the first decoder may include m
2
decoding units each of which performs predetermined logic with respect to the m-bit X-data, wherein the first signal generated by the first decoder addresses a set of m
2
wordlines in the first half of the memory bank. In particular, each of the decoding units includes a logic circuit for performing a predetermined logic operation with respect to the m-bit X-data, and a transmission gate controlled by a set signal provided from an external source, for receiving an output of the logic circuit to generate a signal to address one of the m
2
wordlines of the first half of the memory bank. The second decoder may also include m
2
decoding units each of which performs a predetermined logic with respect to the m-bit X-data and p bits of the fuse data, wherein the second signal generated by the second decoder addresses a set of m
2
wordlines in the second half of the memory bank, and the p bits of the fuse data are corresponding to p blown fuses. In particular, each of the decoding units includes means for performing a predetermined logic operation with respect to the m-bit X-data and the p-bit fuse data, and at least one transmission gate controlled by a set signal provided from an external source, for receiving outputs from the means for performing a predetermined logic operation to generate a signal to address one of the m
2
wordlines in the second half of the memory bank.
The address decoding method of the present invention includes decoding the row address signal to address wordlines in a first half of the memory bank, and decoding the row address signal with fuse information to address wordlines in a second half of the memory bank, wherein the fuse information is determined by a status of fuses associated with wordlines in the memory bank, and the row address signal addresses a pair of wordlines in the memory bank at the same time, and first and second wordlines of the pair of wordlines are in the first half and the second half of the memory bank, respectively. The method may also include the steps of providing redundant wordlines to be replaced with defective wordlines in the memory bank, selecting one of the redundant wordlines that is addre
Chung Phung M.
Infineon - Technologies AG
Stanton Braden
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