Address generation apparatus for turbo interleaver and...

Details Address generation apparatus for turbo interleaver and... Address generation apparatus for turbo interleaver and...

2008-06-10

2008-06-10

Ton, David (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Data formatting to improve error detection correction...

C714S755000

Reexamination Certificate

active

07386766

ABSTRACT:
There is provided an address generation apparatus for one of an interleaver and a deinterleaver in a Wideband Code Division Multiple Access (W-CDMA) system. The apparatus includes an address pair generator for generating an address pair (n, P(n)) in real-time for one of an interleaver operation and a deinterleaver operation that includes inter-row permutation and intra-row permutation. The address pair (n, P(n)) is generated such that, for the interleaving operation, data to be interleaved are read out from the at least one memory device using the P(n) and interleaved data are written into the at least one memory device using the n. Further, the address pair (n, P(n)) is generated such that, for the deinterleaving operation, data to be deinterleaved are read out from the at least one memory device using the n and deinterleaved data are written into the at least one memory device using the P(n).

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Search Report dated Jul. 7, 2004.

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