Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
1999-02-10
2002-02-26
Tu, Christine T. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C711S001000, C365S236000
Reexamination Certificate
active
06351833
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an address generator used for generating addresses required to read out data from a memory. The present invention also relates to a semiconductor device tester incorporating such an address generator.
2. Description of the Related Art
Conventionally, use has been made of various types of testers for testing semiconductor devices such as LSIs (large-scale integrated circuits). In such a tester, a plurality of bit patterns may need to be generated for subjecting a semiconductor device to different kinds of tests.
For generating plural bit patterns, the conventional tester may be provided with a memory arranged to store a plurality of data (bit pattern units). Each of these data has the same bit number and is associated with a particular address in the memory. The conventional tester may also be provided with an address generator controlled by a suitable processor.
In operation, the address generator provides consecutive readout addresses under the control of the processor. These readout addresses are supplied to the memory of the tester. As a result, some of the bit pattern units whose addresses in the memory coincide with the readout addresses are output from the memory. Then, the output bit pattern units are combined to make a bit pattern required for performing a test of the semiconductor device.
The conventional address generator may have an arrangement shown in
FIG. 4
of the accompanying drawings. Specifically, the address generator includes a first latch circuit
32
, a second latch circuit
33
and a counter
34
. The first and the second latch circuits
32
-
33
are associated with a processor
31
(which may be a microcomputer for example), while the counter
34
is associated with a memory
35
.
The processor
31
sets a start address at the first latch circuit
32
while also setting a stop address at the second latch circuit
33
. Then, based on these start and stop addresses, the counter
34
will perform counting at regular intervals.
In the above counting operation, the counter
34
first provides an initial count number which is equal to the start address, and then provides the next count number which is greater than the initial count number by one. Then, the counter
34
provides another count number which is greater than the above-mentioned next count number by one.
Such a procedure is continued until a count number provided by the counter
34
becomes equal to the stop address (maximum count number). Each of the above count numbers (namely, the initial count number, the intermediate count numbers and the maximum count number) is subsequently supplied to the memory
35
as a readout address. As a result, the memory
35
repeatedly outputs a piece of data whose address in the memory coincides with a readout address supplied from the counter
34
. The thus output data are supplied to a terminal
36
.
The conventional address generator has been found disadvantageous in the following points.
With the use of the conventional address generator, the processor
31
needs to reset the start address and the stop address after the counter
34
has finished supplying the first series of readout addresses to the memory
35
. In such an arrangement, the software for operating the processor
31
tends to be unfavorably complicated. In addition, the load on the processor
31
becomes unduly great.
Further, when a low-performance microcomputer is used for the processor
31
, the conventional address generator suffers from the following problem. Supposing that the counter
34
is operated at high speed (based on a clock signal having a frequency of 1-20 MHz for example), the processor
31
may fail to renew the start and the stop addresses at the first and the second latch circuits
32
-
33
since the processing speed of the low-performance processor
31
is not high enough. As a result, the counter
34
will repeatedly generate the same series of readout addresses based on the unaltered start address and stop address.
Even in an instance where the start address and the stop address cannot be renewed, a desired bit pattern may be obtainable from the memory
35
. Specifically, by causing the desired bit pattern as a whole to be stored in the memory
35
, that particular bit pattern can be read out from the memory
35
based on the unaltered start and stop addresses. However, such an arrangement may need an unfavorably great number of addresses in the memory
35
since the entirety of the bit pattern has to be stored in the memory
35
. In other words, the above arrangement requires the memory
35
to have an extremely large storage capacity, which is disadvantageous in terms of costs for example.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention is to provide an address generator which eliminates or reduces the above-described problems.
Another object of the present invention is to provide a semiconductor device tester incorporating such an address generator.
According to a first aspect of the present invention, there is provided an address generator for generating addresses needed to read out data from a memory, the address generator comprising:
a first and a second latch circuits;
a first counter connected to each of the first and the second latch circuits;
a first and a second storages each connected to the first counter; and
a second counter connected to each of the first and the second storages.
With such an arrangement, it is possible to reduce the load on a processor used for controlling the address generator. In addition, programs for operating the processor are advantageously simplified.
According to a preferred embodiment, the first latch circuit is arranged to latch a first start address, while the second latch circuit is arranged to latch a first stop address.
The first counter may perform counting based on the first start address and the first stop address.
The first counter may supply a count number to each of the first and the second storages, the count number supplied by the first counter being obtained from the counting by the first counter.
The first storage may store a plurality of second start addresses, the first storage being arranged to supply one of the second start addresses to the second counter in response to the count number from the first counter.
Likewise, the second storage may store a plurality of second stop addresses, the second storage being arranged to supply one of the second stop addresses to the second counter in response to the count number from the first counter.
Preferably, the second counter may perform counting based on said one of the second start addresses and said one of the second stop addresses.
The second counter may supply a count number to the memory, the count number supplied by the second counter being obtained from the counting by the second counter.
According to a second aspect of the present invention, there is provided a semiconductor device tester comprising:
a processor for controlling the semiconductor device tester;
an address generator provided with a first latch circuit, a second latch circuit, a first counter, a first storage, a second storage and a second counter;
a memory connected to the second counter; and
a wave form processing circuit connected to the memory.
According to a preferred embodiment, the processor comprises a microcomputer.
The memory may comprise a random access memory.
According to the preferred embodiment, the processor supplies a first start address to the first latch circuit while also supplying a first stop address to the second latch circuit.
Advantageously, each of the first and the second latch circuits may be connected to the first counter, the first counter being connected to each of the first and the second storages, each of the first and the second storages being connected to the second counter.
Other objects, features and advantages of the present invention will become clearer from the detailed description of preferred embodiments given below with reference to the acco
Merchant & Gould P.C.
Rohm & Co., Ltd.
Tu Christine T.
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