Addressable tap domain selection circuit with TDI/TDO...

Details Addressable tap domain selection circuit with TDI/TDO... Addressable tap domain selection circuit with TDI/TDO...

2007-12-11

2007-12-11

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C324S763010

Reexamination Certificate

active

11292643

ABSTRACT:
This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the invention include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations.

REFERENCES:
patent: 5222068 (1993-06-01), Burchard
patent: 5574730 (1996-11-01), End, III et al.
patent: 5754879 (1998-05-01), Johnston

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