Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2007-04-10
2007-04-10
Dildine, R. Stephen (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S763000, C714S766000
Reexamination Certificate
active
10710066
ABSTRACT:
A memory system provides data error detection and correction and address error detection. A Single-byte Error-Correcting/Double-byte Error-Detecting (SbEC/DbED) code with the byte being a 4-bit nibble is used to detect up to 8-bit errors and correct data errors of 4 bits or less. Rather than generating address parity, which is poor at detecting even numbers of errors, a cyclical-redundancy-check (CRC) code generates address check bits. A 32-bit address is compressed to just 4 address check bits using the CRC code. The 4 address check bits are merged (XOR'ed) with two 4-bit nibbles of the data SbEC/DbED code to generate a merged ECC codeword that is stored in memory. An address error causes a 2-nibble mis-match due to the redundant merging of the 4 address check bits with 2 nibbles of data correction code. The CRC code is ideal for detecting even numbers of errors common with multiplexed-address DRAMs.
REFERENCES:
patent: 3231858 (1966-01-01), Tuomenoksa et al.
patent: 3963908 (1976-06-01), Das
patent: 4672609 (1987-06-01), Humphrey et al.
patent: 5099484 (1992-03-01), Smelser
patent: 5226043 (1993-07-01), Pughe, Jr. et al.
patent: 5345582 (1994-09-01), Tsuchiya
patent: 5691996 (1997-11-01), Chen et al.
patent: 5761221 (1998-06-01), Baat et al.
patent: 5768294 (1998-06-01), Chen et al.
patent: 5841795 (1998-11-01), Olarig et al.
patent: 5978953 (1999-11-01), Olarig
patent: 6003144 (1999-12-01), Olarig et al.
patent: 6134699 (2000-10-01), Steenburgh et al.
patent: 6308297 (2001-10-01), Harris
patent: 6457067 (2002-09-01), Byers et al.
patent: 6457154 (2002-09-01), Chen et al.
patent: 6480975 (2002-11-01), Arimilli et al.
patent: 6539504 (2003-03-01), Knefel
patent: 6574774 (2003-06-01), Vasiliev
patent: 2002/0007476 (2002-01-01), Tsuyoshi
patent: 2003/0218816 (2003-11-01), Katoh et al.
patent: 03186954 (1991-08-01), None
patent: 05181757 (1993-07-01), None
patent: 2000099409 (2000-04-01), None
patent: WO 9002372 (1990-03-01), None
Bergey, A. L.; Checking Algorithm for Two Byte RAM with One or Two Byte Access; Apr. 1, 1994; IBM Technical Disclusure Bulletin, vol. 37, No. 04B; pp. 655-658.
Henle, et al.; Error Correcting Address Technique; May 1, 1970; IBM Technical Disclusure Bulletin, vol. 12, No. 12, pp. 2071-2072.
Kaufman, D. R.; Address Error Detection for Memory Using SEC/DED with Processor Using Byte Parity Error Detection; Apr. 1, 1982; IBM Technical Disclusure Bulletin, vol. 4, p. 6122.
Derwent abstract of inventer's certificate SU 1501122 A (Ivakhiv et al.).
P. Koopman and T. Chakravarty, “Cyclic Redundancy Code (CRC) Polynomial Selection for Embedded Networks”,Int'lConf. On Dependable Sys. and Networks., DSN-2004, pp. 1-10, 2004.
S. Kaneda and E. Fujiwara, “Single Byte Error Correcting—Double Byte Error Detecting codes for Memory Systems”,IEEE Trans. Computers, vol. C-31, No. 7, pp. 596-602, Jul. 1982.
Auvinen Stuart T.
Azul Systems, Inc.
Dildine R. Stephen
g Patent LLC
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