Built-in self test for speed and timing margin for a source...

Built-in self test system and method for high speed clock...

Built-in self test system and method for two-dimensional...

Built-in self testing circuit with fault diagnostic capability

Built-in self verification circuit for system chip design

Built-in self-analyzer for embedded memory

Built-in self-repair of semiconductor memory with redundant...

Built-in self-repair wrapper methodology, design flow and...

Built-in self-repairable memory

Built-in self-test (BIST) architecture having distributed...

Built-in self-test (BIST) for high performance circuits

Built-in self-test (BIST) of memory interconnect

Built-in self-test apparatus

Built-in self-test arrangement for integrated circuit memory...

Built-in self-test circuit for phase locked loops, test...

Built-in self-test circuit for read channel device

Built-in self-test controlled by a token network and method

Built-in self-test emulator

Built-in self-test for multi-channel transceivers without...

Built-in self-test for multi-channel transceivers without...