Built-in self-test controlled by a token network and method

Details Built-in self-test controlled by a token network and method Built-in self-test controlled by a token network and method

1997-10-07

2001-05-22

Iqbal, Nadeem (Department: 2785)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S030000

Reexamination Certificate

active

06237123

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a token passing network and a method for scheduling built-in self-tests of one or more self-testing memory, Random Logic and Embedded core elements within a digital circuit.
BACKGROUND OF THE INVENTION
This invention relates to a token passing network and a method for scheduling Built-In Self-Test (BIST) in memory elements based on: a matrix and ring structure of resource controllers, e.g., Scheduled BIST Resource Interface controllers (SBRICs), controlling the memory elements; executing BIST in parallel, with or without stages, to optimize efficiency of such testing; and passing a token to initiate processing between sets of SBRICs in the matrix via a level signal rather than a pulse signal to ensure that the token is received.
The scale of integration of memory elements, for example Regular Structure semiconductor elements (such as RAMs, ROMs, CAMs, FIFOs or Embedded Cores) and Random Logic elements, has increased in modern digital circuits in order to increase the circuit's functionality. The increased density has also heightened the difficulty of testing such circuits with conventional external testing machines. Consequently, much effort has been devoted to “Design for Testability” approaches, including designing memory elements with BIST capability, that is, the capability to test themselves.
However, BIST capability within memory elements of Very Large Scale Integrated (VLSI) circuits has not eliminated the difficulty of testing. The testing of a VLSI circuit including a variety of BISTed elements (i.e., elements having BIST capability) requires that an interface be provided within the circuit to couple control signals between a test controller and the BISTed memory elements to initiate and schedule BIST efficiently.
One approach is described in U.S. Pat. No. 5,570,374 to Yau et al., which is assigned to Lucent Technologies, Inc. This patent is incorporated in its entirety herein by reference. This patent provides a BIST network, including at least two BISTed elements (for example, each comprising a RAM, ROM, FIFO or a Random Logic element). The control network comprises at least one SBRIC which controls one or more Regular Structure BISTed memory elements (such SBRIC is hereinafter referred to as the SBRIC_RS, and the memory elements with Regular Structure BIST are hereinafter referred to as RSB elements). In addition, the network comprises a plurality of SBRIC_RSs serially coupled in a daisy chain. The first SBRIC_RS in the chain serves to initiate self-testing of a first group of RSB elements which are coupled to the SBRIC_RS in parallel. Each successive SBRIC_RS in the chain is responsive to a control signal generated by a previous SBRIC_RS in the chain and serves to initiate self-testing of the RSB elements in the corresponding successive group associated with that SBRIC_RS so that groups of RSB elements are tested in sequence. In addition, since each of the SBRIC_RSs runs on the same clock, they run on different clocks than the RSB elements they control.
There are several disadvantages of the approach described in the above patent. The serial coupling of the SBRIC_RSs limits processing to a single SBRIC_RS at a time. We have found that due to limitations on the number and type of RSB elements a single SBRIC_RS can control, this feature reduces the network's efficiency in testing a large number of different RSB elements at one time.
Another disadvantage is that the network is limited to one pass for each SBRIC_RS. That is, at the end of processing for the last SBRIC_RS in the serial daisy chain, no further processing by any SBRIC_RS can occur. Accordingly, where BIST testing includes a waiting period (for example, for retention testing), there is no means for initiating the processing of another one of the SBRIC_RS elements during the waiting period. In addition, where the BIST of more than one SBRIC_RS includes a waiting period, each SBRIC_RS must implement a waiting period separately rather than applying a single such waiting period to several SBRIC_RSs.
Since each of the SBRIC_RSs runs on the same clock, they do not run on the same clock as their RSB elements. This results in asynchronous processing between each SBRIC_RS and its RSB elements. As a result, we have found that the signals transmitted between a SBRIC_RS and its group of RSB elements may be lost.
An additional disadvantage is that the network's behavior cannot be modified once it is implemented. For example, one or more SBRIC_RSs cannot be disabled from processing their RSB elements in order to improve efficiency of the network. Such functionality can apply where a SBRIC_RS in position after others in the chain enters its fail state to indicate that at least one of its RSB elements failed BIST testing and the faulty RSB element is replaced. However, each of the SBRIC_RSs must rerun BIST rather than limiting BIST processing to solely the SBRIC_RS element having the replaced RSB element.
Therefore, there is a need to improve a BIST control network for scheduling the self-testing of a plurality of different types of BISTed memory elements.
SUMMARY OF THE INVENTION
This invention relates to a token passing network, called a Universal BIST Scheduler (UBS), and a method for scheduling BISTed memory elements based on: executing BIST in parallel multiple stages in order to optimize the efficiency of continuous processing and to apply a single waiting period to multiple SBRIC_RSs where, for example, BIST includes retention testing; dividing resource controllers or SBRIC_RSs corresponding to one or more RSB elements into a matrix such that each SBRIC_RS executes the BIST of its memory elements concurrently and/or successively depending on the SBRIC_RS's position in the matrix; and passing a token to initiate processing of a set of SBRIC_RSs in the matrix through a level signal rather than a pulse signal in order to ensure that the signal is not lost.
More particularly, the UBS according to an illustrative embodiment of our invention can include a plurality of SBRIC_RSs organized into a matrix where each SBRIC_RS controls one or more (or a group of) RSB elements through a Regular Structure BIST controller (hereinafter referred to as a RSBCtl).
One aspect of our invention is that BIST testing for each RSB element can be executed in multiple stages or tests to complete BIST testing, as described in our copending application Ser. No. 09/944,716 filed Oct. 7, 1997 filed currently herewith, and incorporated herein by reference wherein each stage, a group of SBRIC_RSs operate in parallel. For example, in the illustrative embodiment of our invention, there are three stages for BIST: during the first stage, a BIST algorithm is implemented in parallel by a plurality of elements according to the particular type of RSB element and the results of such testing are reflected in a “test signature” for each RSB element. After the first stage and before the second stage, retention testing is initiated. Retention testing identifies retention faults in the RSB elements or the loss of a data value stored in a memory cell over time. A retention fault occurs as a result of a leakage of one or more bits in a previously written cell or word after a period of time. In order to detect such faults, a waiting period sufficient to allow for leakage where such fault exists must occur. After the BIST algorithm has been implemented in the first stage and before the second stage, the waiting period is applied to each RSB element. During the second stage, the memory cells of each RSB element are reread to test whether after the waiting period, the binary values resulting from BIST testing during the first stage have been retained. The second stage comprises a retention test. In addition, during the second stage, the values in the memory cells are toggled such that the bit pattern in the memory cells is the complement of the bit pattern resulting from BIST testing. In between the second and third stages, another waiting period is implemented for retention testing of the

Affiliated with

Also associated with

Rating

Built-in self-test controlled by a token network and method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Built-in self-test controlled by a token network and method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Built-in self-test controlled by a token network and method will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2532631