Built-in self test for speed and timing margin for a source...

Details Built-in self test for speed and timing margin for a source... Built-in self test for speed and timing margin for a source...

2001-03-23

2004-07-06

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C324S073100, C326S016000

Reexamination Certificate

active

06760873

ABSTRACT:

BACKGROUND
This invention generally relates to devices and methods for testing a source synchronous IO interface, and more specifically relates to a built-in self test implementation for testing a source synchronous IO interface.
The timing requirements for high speed source synchronous IO (SSIO) interfaces are highly demanding for existing and even future automatic test equipment (ATE). The challenges are driven in several directions. The most challenging is the accuracy requirement. Traditionally, IO pins are individually specified, characterized, and tested for setup and hold times for input pins and pin-to-pin delay for output pins. For SSIO interfaces, timing is specified for a group of pins including data and clock pins. For a receiver (RX port), the setup and hold times are with respect to the clocks that are part of the port. The clocks themselves do not have fixed timing, which makes measuring the data pins against a fixed reference harder. Secondly and more importantly, the aggregate setup and hold times are already in the range of less than 150 ps. Today's high accuracy ATE can achieve edge placement accuracy of +/−100 ps. So to accommodate the ATE pin timing inaccuracy such that there is no unnecessary yield loss due to ATE inaccuracy, the setup and hold times can only be tested at close to twice the required values. A third consideration is that since there can be a large number of instantiations of SSIO interfaces in VLSI chips, the ATE would have to support not only high accuracy, but also a large number of high accuracy pins. Consequently, the ATE required for testing such chips could be quite costly.
SSIO interfaces have been used in high performance VLSI chips. The known techniques in use in the industry to test SSIO interfaces fall into several categories. The most widely used is probably functional tests. Functional tests rely on the ATE to provide stimulus to a device under test (DUT), and to sample output values from the DUT. This technique can be used to test the full functional specification of the SSIO interface. However, as mentioned above, this technique can no longer meet the increasingly high speed and accuracy requirements of today's SSIO interfaces.
Another technique in use is a system test approach. This technique relies on previously characterized, or so called “golden”, devices and board to provide stimulus to and sample outputs from the DUT. This technique provides that speed can be measured effectively in a realistic system environment. However, it is not easy to perform accurate DC tests as well as AC timing margin tests. The accuracy can also be affected by how stable the “golden” devices are in a production environment and throughout production cycles. Additionally, this technique usually requires more than one production test pass.
A schematic diagram of a conventional transmitter (TX port)
10
is shown in FIG.
1
. Shown in
FIG. 2
are bit slices relating to the conventional TX port
10
shown in FIG.
1
. As shown in
FIGS. 1 and 2
, a conventional TX port
10
includes transmitter (TX) logic
12
, output buffers
14
and output pads or pins
16
. As shown in
FIG. 1
, a conventional TX port
10
also includes a transmitter (TX) boundary scan cell
18
. The TX logic
12
includes a plurality of flip flops
20
and multiplexers
22
(see specifically
FIG. 2
which shows a portion of the TX logic
12
in more detail). The TX logic
12
is configured to receive data input signals
24
and supply data and clock output signals
26
to the output buffers
14
and output pins
16
.
As shown in
FIGS. 1 and 2
, a conventional TX port
10
does not include any built-in self test logic. The structure of a conventional receiver (RX port) is much the same, and does not include any built-in self test logic. Instead, the signals at the IO pins (
16
in
FIGS. 1 and 2
) of a conventional SSIO interface must be tested using one of the foregoing techniques, which presents disadvantages, some of which have been discussed above.
OBJECTS AND SUMMARY
A general object of an embodiment of the present invention is to provide a built-in self test implementation for testing the speed and timing margins of the IO pins of a SSIO interface.
Another object of an embodiment of the present invention is to provide a test implementation which provides that a high speed SSIO interface can be tested in production with better accuracy than conventional ATE can achieve.
A further object of an embodiment of the present invention is to provide a test implementation which provides that the high cost associated with high accuracy ATE can be avoided.
Still yet another object of an embodiment of the present invention is to provide a built-in self test implementation which is designed to be self-contained in each SSIO interface.
Another object of an embodiment of the present invention is to provide a versatile built-in self test implementation which provides that the test feature is portable to all VLSI chips that instantiate the ports.
A further object of an embodiment of the present invention is to provide a built-in self test implementation which provides that all the built-in self test logic is implemented inside the hard macro of a SSIO interface.
Another object of an embodiment of the present invention is to provide a test implementation which is designed not only for production tests but also to be used in SSIO characterization.
A further object of an embodiment of the present invention is to provide a test implementation which is designed not only for production tests but also to be useful in SSIO debug applications.
Yet another object of an embodiment of the present invention is to provide a test implementation for a SSIO interface which is designed to be a single-pass production technique.
Briefly, and in accordance with at least one of the foregoing objects, an embodiment of the present invention provides a SSIO interface, such as a TX or RX port, which includes built-in self test logic configured to test the speed and accuracy of data and clock signals of the interface and generate at least one output signal depending on the result of the test.
Preferably, the built-in self test logic includes a pseudo-random pattern generator which is configured to generate input sequences. Buffers are connected to the IO pins and receive the input sequences. The buffers are also connected to multiple input signature registers, and the multiple input signature registers are configured to receive the input sequences from the pseudo-random pattern generator and generate signatures. Preferably, the pseudo-random pattern generator includes two sets of linear feedback shift registers and two sets of multiple input signature registers are provided—a first set corresponding to a rising edge, and a second set corresponding to a falling edge. Comparators are provided to compare the signatures generated by the pseudo-random pattern generator to expected vector values and generate at least one pass/fail output signal. Preferably, at least one programmable delay cell is disposed between each buffer and the multiple input signature registers, and the programmable delay cells provide that propagation delays can be set either externally or by using on-chip registers, such as JTAG registers. By adjusting the relative positions of an edge of a clock signal and an edge of a data signal, timing margin tests can be conducted.
Preferably, a standalone calibration circuit is initially connected to the programmable delay cells and the calibration circuit is configured to determine the actual delay associated with the programmable delay cells. Thereafter, the actual delay is taken into account when performing the timing margin tests. Preferably, the comparators which are included in the logic include a first comparator connected to the pseudo-random pattern generator and configured to receive a stop pattern vector signal, wherein the first comparator is in communication with a controller, and the controller is configured to interrupt the test in response to the first comparator rece

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