Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-12-21
2004-12-21
Moise, Emmanuel L. (Department: 2136)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S704000, C714S742000, C714S814000, C714S815000, C375S219000, C375S224000, C370S249000, C370S366000
Reexamination Certificate
active
06834367
ABSTRACT:
PRIOR FOREIGN APPLICATION
This application claims priority from European patent application number 99480131.4, filed Dec. 22, 1999, which is hereby incorporated herein by reference in its entirety.
TECHNICAL FIELD
The present invention relates to systems for testing clock and data recovery circuits, and more particularly to a built-in self test system.
BACKGROUND ART
In digital systems, digital data is typically handled with an associated clock signal. The clock provides timing necessary to allow digital circuitry to operate on digital data. When data are transmitted over a communications link, it is generally inefficient to also transmit the associated clock signal. This inefficiency has led to communications systems which transmit the data alone without the clock. Therefore, it is typical for fiber optic communication links to require that the clock signal at the receiving end of the link be extracted from the incoming data signal. To obtain the necessary clock at the receiving end, these systems employ clock and data recovery circuits. The clock and data recovery circuit derives the clock signal from the received digital data. Conventional clock and data recovery circuits are often implemented using phase-locked loops. In phase-locked loops, a reference clock is generated at the frequency of the received data using a voltage controlled oscillator (VCO). The phase-locked loop is often integrated onto a single chip along with logic circuits providing other link adapter functions.
In addition to clock recovery circuits, communications links often utilize serializers and deserializers circuits. Serializers on the transmitting side serialize the parallel data in a bit stream. Deserializers at the receiving end parallelize the serial data stream transmitted over the communications link. These parallel data are typically defined by bytes or words that make up the serial stream.
To eliminate defects from integrated circuits including logic circuits a well-known method consists to place observation latches (the famous LSSD latches) which are connected together to allow to scan out each signal which is generated internally. Test patterns sequences are performed at wafer level and if responding patterns do not match the test patterns, the failed circuits are sorted. Unfortunately this method cannot be used to detect defects in the analog circuits.
Conventional methods to test analog components consist in verifying the functionality of the analog circuitry by way of an external test equipment. Such method need that the chip be previously encapsulated before being tested at board level. The general state of the prior art with respect to solving the aforementioned testing problem may be best illustrated and understood with reference to the several patents to be described immediately hereinafter.
In U.S. Pat. No. 5,295,079 from Wong a digital testing system for very high frequency PLLs is proposed. The testing system allows the test of a PLL connected to an external digital tester via a bi-directional bus. The digital tester is an intelligent digital hardware that configures the PLL and extracts and interprets data from the PLL.
In U.S. Pat. No. 5,729,151 from Zoerner, the test of a phase lock loop within an integrated circuit is performed by an external testing device having access to an address/data bus coupled to both the PLL and a timer module which is utilized as a frequency counter for counting the number of clock pulses outputted from the PLL.
The aforementioned conventional methods employ an external testing equipment to test the PLL. Whereas such solutions are efficient to test high frequency PLLs, they are heavy in terms of cost and people, and in addition the permanent performance evolution of the products requires that the test equipment be adapted.
Alternative methods consist in using Built-in Self-Test (BIST) circuits.
In U.S. Pat. No. 5,802,073 from Platt, a built-in self-test (BIST) system for testing a network interface integrated circuit is disclosed. The BIST includes a random number generator to generate test data, and to monitor data going from a receiver of the network interface back to the BIST. The data is compressed into one number and compared with a predetermined signature in a signature analyzer. The BIST uses a functional system block for in-system diagnostic at system speed at a functional level as opposed to gate level.
In U.S. Pat. No. 5,835,501 from Dalmia, a built-in self-test circuit is provided to perform jitter tolerance tests on a clock and data recovery unit by using a pseudo-random data generating apparatus. The test is comprised of the steps of generating a jitter clock, using the jitter clock to generate a test data stream, feeding the test data stream to the clock and data recovery unit and determining the number of bits errors in the recovered data stream. This method requires that all the recovered bits be examined to determine the famous Bit Error Rate (BER) which is thus a time consuming solution.
SUMMARY OF THE INVENTION
Accordingly, it would be desirable to be able to provide a functional wafer level test system and method which allows full fault coverage of a clock and data recovery circuit.
The present invention provides a built-in self test apparatus for testing a clock and data recovery circuit which operates with high speed phase lock loop. The built-in circuit comprises data generating means for generating a test data byte and serializing means coupled to the data generating means for converting the test data byte into serial test data. The clock and data recovery means are coupled to the output of the serializing means for recovering the clock and test data from the serial test data. A deserializing means coupled to the output of the clock and data recovery means converts the recovered serial test data into a recovered test data byte, and analyzing means connected to the output of the deserializing means compares the recovered test data byte to the initial test data byte.
In a commercial application, the invention is preferably used in a high speed telecommunication framer which fulfill the requirements of the SONET technology.
It is another object of this invention to provide a method for testing a clock and data recovery circuit comprising the steps of:
generating an initial test data byte,
inputting the test data byte to a serializer for conversion into serial test data,
sending the serial test data to the clock and data recovery circuit for recovering the clock and the test data,
inputting the recovered test data to a deserializer for conversion into a recovered test data byte, and
comparing the recovered test data byte to the initial test data byte.
REFERENCES:
patent: 5295079 (1994-03-01), Wong et al.
patent: 5381085 (1995-01-01), Fischer
patent: 5729151 (1998-03-01), Zoerner et al.
patent: 5787114 (1998-07-01), Ramamurthy et al.
patent: 5835501 (1998-11-01), Dalmia et al.
patent: 5956370 (1999-09-01), Ducaroir et al.
patent: 6201829 (2001-03-01), Schneider
patent: 6215835 (2001-04-01), Kyles
Bonneau Dominique P.
Hauviller Philippe
Vallet Vincent
Cutter, Esq. Lawrence D.
Heslin Rothenberg Farley & & Mesiti P.C.
Moise Emmanuel L.
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