Built-in self-test circuit for phase locked loops, test...

Details Built-in self-test circuit for phase locked loops, test... Built-in self-test circuit for phase locked loops, test...

2007-10-16

2007-10-16

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S731000

Reexamination Certificate

active

10841981

ABSTRACT:
A built-in self-test circuit for phase locked loops includes a measurement circuit for measuring outputs of the phase locked loops, and receiving as inputs a plurality of external test signals. At least one module includes a scan chain for storing the test signals for programming the phase locked loops and the measurement circuit.

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patent: 6779144 (2004-08-01), Hayashi et al.
patent: 2001/0054166 (2001-12-01), Fukuda
Sunter et al., Bist for Phase-Locked Loops in Digital Applications, Proceedings International Test Conference 1999, ITC' 99, Atlantic City, NJ, Sep. 28-30, 1999, International Test Conference, New York, IEEE, US, vol. Conf. Sep. 30, 1999, pp. 532-540, XP000928868.

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