Built-in self-test arrangement for integrated circuit memory...

Details Built-in self-test arrangement for integrated circuit memory... Built-in self-test arrangement for integrated circuit memory...

2007-10-02

2007-10-02

Chung, Phung My (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S734000, C714S718000, C714S706000, C714S763000, C365S201000

Reexamination Certificate

active

10918813

ABSTRACT:
An integrated circuit has a built-in self-test (BIST) arrangement (60). The built-in self-test arrangement includes a read only memory (ROM), (410) that stores test algorithm instructions. A Rom logic circuit (410) receives an instruction read from the read only memory and produces a group of output signals dependent upon the instruction. A BIST register420receives and stores the group of output signals from the logic circuit for controlling self-test of the integrated circuit.

REFERENCES:
patent: 5327363 (1994-07-01), Akiyama
patent: 5481671 (1996-01-01), Fujisaki
patent: 5548553 (1996-08-01), Cooper et al.
patent: 5568437 (1996-10-01), Janal
patent: 5588006 (1996-12-01), Nozuyama
patent: 5617531 (1997-04-01), Crouch et al.
patent: 5640354 (1997-06-01), Jang et al.
patent: 5640404 (1997-06-01), Satish
patent: 5640509 (1997-06-01), Balmer et al.
patent: 5661729 (1997-08-01), Miyazaki et al.
patent: 5661732 (1997-08-01), Lo et al.
patent: 5689466 (1997-11-01), Qureshi
patent: 5875153 (1999-02-01), Hii et al.
patent: 5923599 (1999-07-01), Hii et al.
patent: 5936900 (1999-08-01), Hii et al.
patent: 5953272 (1999-09-01), Powell et al.
patent: 5959912 (1999-09-01), Powell et al.
patent: 5991213 (1999-11-01), Cline et al.
patent: 6014336 (2000-01-01), Powell et al.
patent: 6353563 (2002-03-01), Hii et al.
patent: 6418077 (2002-07-01), Naven
patent: 2002/0089887 (2002-07-01), Hii et al.
Takeshima et al.; A 55-ns 16-Mb DRAM with Built-in Self-Test Function Using Microprogram ROM; IEEE Journal of Solid-State Circuits, vol. 25, No. 4, Aug. 1990; pp. 903-911.
Takeshima et al.; A 55ns 16Mb DRAM; 1989 IEEE International Solid-Stae Circuits Conference; Feb. 17, 1989; pp. 246-247.
Voss et al.; A 14-ns 256K×1 CMOS SRAM witih Multiple Test Modes; IEEE Journal of Solid-State Circuits, vol. 24, No., Aug. 1989; pp. 874-880.
Miyaji et al.; A Multibit Test Trigger Circuit for Megabit SRAMs; IEEE Journal of Solid-State Circuits, vol. 25, No. 1, Feb. 1990; pp. 68-71.
Koike, et al. A BIST Scheme Using Microprogram ROM For Large Capacity Memories, 1990 International Test Conference, Paper 36.1, pp. 815-822.
Koike, et al., BIST Circuit Macro Using Microprogram ROM for LSI Memories, IEICE Trans. Electron. vol. E78-C, No. 7, Tokyo, Japan, pp. 838-844.
Franklin, et al., Built-in Self-Testing of Random-Access Memories, 8153 Computer, Oct. 23, 1990, No. 10, Los Alamitos, CA, pp. 45-56.

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