Built-in self testing circuit with fault diagnostic capability

Details Built-in self testing circuit with fault diagnostic capability Built-in self testing circuit with fault diagnostic capability

2011-06-14

2011-06-14

Ton, David (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S719000

Reexamination Certificate

active

07962821

ABSTRACT:
A semiconductor integrated circuit includes: a memory collars including: a memory cell; a fetch register that is configured to fetch data as a first fetch data; a comparing unit that is configured to compare the first fetch data with an expected value; a failure detecting signal output unit that is configured to receive the compared result and output a failure detecting signal; and a BIST circuit including: a BIST control unit that is configured to output an instruction and output a BIST status; a shift controller that is configured to receive a first clock signal, the BIST status signal, and the failure detecting signal and output sift enable signal; a shift counter that counts the number of clock pulses on the first clock signal; a first storage register that is configured to receive the first clock signal and the shift enable signal, and a second storage register that is configured to receive a second clock signal.

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Japanese Office Action dated Jan. 5, 2010 corresponding to U.S. Appl. No. 12/199,181, filed Aug. 27, 2008.

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