Built-in self verification circuit for system chip design

Details Built-in self verification circuit for system chip design Built-in self verification circuit for system chip design

2000-08-02

2004-01-06

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S734000

Reexamination Certificate

active

06675337

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 89107511, filed Apr. 21, 2000.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a built-in self-verification (BISV) circuit. More particularly, the present invention relates to a built-in self-verification circuit for system chip design. The BISV circuit not only can be applied to test system chip design during integration, but also can used to detect common design errors. Moreover, the BISV circuit can be applied to test out functional uniformity of intellectual property (IP) based on the electronic design automation (EDA) model.
2. Description of Related Art
Trend in the development of system chip design offers some challenges to design verification and testing. The basic functional block of system chip is generally referred to as reusable design or IP. Built-in testing and verification functions are regarded as a major aspect in accelerating the process of verifying a system chip design. However, the conventional stuck-at fault model of testing pattern generation is mainly used for detecting manufacturing faults. If the operation is used for testing functions in system integration, time is wasted in testing already verified IP blocks. Moreover, conventional automatic test pattern generator (ATPG) can only be applied to circuit having a logic netlist model. Thus, circuit function meeting the design specification is assumed when the test pattern is generated. Hence, the test pattern of stuck-at fault based on the interconnection of internal devices is incapable of verifying the design specification. Another method includes the use of a pseudo-random number generator to produce a functional verification input pattern. Although potentially the method has better functional coverage, testing time and length of the test pattern tend to increase in proportional to the number of input ports.
Built-in self-testing (BIST) and related technical considerations can be found in the following disclosed U.S. Patents:
(1) U.S. Pat. No. 5,960,009 titled “Built-in shelf test method and apparatus for booth multipliers”;
(2) U.S. Pat. No. 5,923,677 titled “Method and apparatus for detecting failures between circuits”;
(3) U.S. Pat. No. 5,831,991 titled “Methods and apparatus for electrically verifying a functional unit contained within an integrated circuit”;
(4) U.S. Pat. No. 5,751,737 titled “Boundary scan testing device”;
(5) U.S. Pat. No. 5,668,817 titled “Self-testable digital signal processor and method for self-testing of integrating circuits including DSP data paths”;
(6) U.S. Pat. No. 5,938,784 titled “Linear feedback shift register, multiple input signature register, and built-in self test circuit using such registers”;
(7) U.S. Pat. No. 5,790,562 titled “Circuit with built-in test and method thereof”.
Careful analysis of the aforementioned U.S. patents reveals some major differences compared with the structural design proposed according to this invention. The majority of the cases aim at saving a few circuit devices and reducing area occupation when built-in testing circuit is integrated with the original design. However, a different kind of detachable built-in testing circuit and method, as well as a different corresponding structure for generating test pattern based on detecting input/output sequence errors are proposed in this invention.
The so-called boundary scan technique is commonly used in design verifications. The characteristics of such techniques differ from the structure proposed in this invention in two major aspects:
(1) Boundary scan technique usually does not embed a test pattern generating circuit with device under test (DUT which also known as pre-designed and pre-verified functional block in system chip design); and
(2) Boundary scan technique is based on serial transmission. Hence, the testing is designed around inter-block communication.
On the other hand, the proposed invention has no limitations during testing or operating in normal mode. Blocks can be connected either serially or parallelly depending on the actual requirement in the system chip design. Hence, through this invention, any section of lines in the figure can represent sequentially connected lines or parallel transmission lines.
Built-in self-testing (BIST) technique aims at finding defects in the circuit during manufacturing. Concepts behind the BIST technique can be illustrated using FIG.
1
.
FIG. 1
is a schematic diagram showing the basic structure of a conventional BIST circuit. As shown in
FIG. 1
, the BIST circuit
100
includes a pseudo-random pattern generator (PRPG)
102
, a multiplexer (MUX)
104
, a circuit-under-test (CUT)
106
and an output response analyzer (ORA)
108
. Conventional clock pulse and control signals are omitted in the figure for simplification.
In normal execution state, the primary input (PI) and the PRPG circuit
102
in the testing mode are connected to the input terminal of the CUT circuit
106
via the multiplexer
104
. Aside from connecting to the primary output, the CUT circuit
106
also connects to the output response analyzer
108
so that any deviation of the output value from the CUT
106
and the expected value can be determined. In general, the ORA
108
is also responsible for compressing output data so that the less space is required for storing test output data.
A conventional BIST circuit aims mainly at detecting faults in manufacturing. Consequently, some common design faults may not be found when integrating the virtual components of system chips or functional blocks commonly referred to as IP. In the process of integrating with the already tested IP design blocks, the most common problems are unlikely to be errors in the design of individual functional block. Rather, most problems will occur in the configuration of connecting lines between the blocks. For example, the bits in a bus should be in the sequential order (31:0) or (0:31). This type of design fault is often referred to as port order fault (POF) for input or output. Characteristics of POF can be obtained from article [1] below.
[1]: Shing-Wu Tung and Jing-Yang Jou, “A Logical Fault Model for Library Coherence Checking”, Journal of Information Science and Engineering, Vol.14 No. 3, pp. 567-586, September 1998.
FIGS. 2A through 2D
are block diagrams showing four 4-bit adders having no fault, a first port order fault, a second port order fault and a third port order fault respectively. In the figures, C
IN
represents signal input terminal, C
OUT
represents signal output terminal, A
0
-A
3
and B
0
-B
3
represent input ports and S
0
-S
3
represent output ports.
The meanings implied in
FIGS. 2A-2D
are as follows:
(1)
FIG. 2A
indicates a no-fault condition: the ordering of the output terminals C
IN
and C
OUT
and input/output ports A
0
-A
3
, B
0
-B
3
and S
0
-S
3
are correct;
(2)
FIG. 2B
shows a first port order fault (POF): the ordering between the input terminal C
IN
and the output terminal C
OUT
is wrong;
(3)
FIG. 2C
shows a second POF: the ordering of the input ports A
0
-A
3
is wrong; and
(4)
FIG. 2D
shows a third POF: the ordering of the output ports S
0
-S
3
is wrong.
The first type of POF can be checked by generating a random test pattern as indicated in article [1]. Hence, integrated verification of the chip should target the two remaining types of POFs.
In general, the most common IP integration faults include interface design errors, faulty/short-circuiting/erroneous connections (for example: POF), mismatch communication protocol and so on.
FIG. 3
is a block diagram showing the theory behind the detection of port order failure. Besides detecting errors in the connecting line
133
between pre-designed blocks, the aforementioned integration faults can also be found. A test pattern T is fed to the input terminal of the functional block (BLK
1
)
130
, and then a response R is obtained from the output terminal of a subsequent functional block (BLK
2
)
132
. The response from the se

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