Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-08-07
2004-04-20
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S742000
Reexamination Certificate
active
06725408
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention generally relates to testing of transceivers. More specifically, the present invention relates to a method and device for implementing a built-in self-test for multi-channel transceivers.
In modern data networks, data are typically transmitted in high volume at a high transmission rate over long distances. Since the quality of the data signals degrades proportionally with the length of a transmission line, circuits known as tansmitter-receivers or transceivers are usually placed along a transmission line at certain predetermined locations to boost or rebroadcast the data signals to maintain their quality. Thus, due to the nature of their operation, transceivers need to be monitored and tested to ensure that the boosted data signals they produce are indeed accurate versions of the original signals.
FIG. 1
is a simplified block diagram showing a conventional transceiver circuitry which typically includes a clock/data recovery circuit
10
, a demultiplexer
12
and a multiplexer
14
. The testing of the transceiver is usually done in the following manner. External circuitry
8
produces a test signal as input to the multiplexer
14
. The test signal is transmitted as a frame via multiple input channels
18
into the multiplexer
14
. The test signal is then serialized by the multiplexer
14
and transmitted through a single multiplexer output channel
16
to the clock/data recovery circuit
10
. The clock/data recovery circuit
10
recovers the test signal and feeds the recovered test signal into the demultiplexer
12
. One function of the demultiplexer
12
is to parse the recovered data and direct them into various output channels
20
(i.e. deserialize the data stream). The collective output from these various output channels
20
is then checked by external circuitry
6
against the test signal to determine whether the transceiver is functioning properly.
During the course of transmission from the multiplexer
14
through the clock/data recovery circuit
10
to the demultiplexer
12
, it is not unusual to have a collective shift in the test signal causing the relative position of the entire test signal to change without affecting the integrity of the test signal. In other words, the beginning of the test signal frame which is transmitted via one input channel of the multiplexer
14
may not always come out at precisely the corresponding output channel of the demultiplexer
12
. For example, the beginning of the test signal frame transmitted via the first multiplexer input channel may not come out at the corresponding first demultiplexer output channel. Thus, while the contents or bits within the frame may have been transmitted correctly, a shift in the frame position may lead to an erroneous conclusion that the transceiver is malfunctioning. In order to avoid this situation, a “framer” circuit, which is commonly known in the art, is typically employed to accurately align or “frame” the initial test signal and the output received from the demultiplexer
12
before the two signals are compared.
Framer circuits that must keep track of signal timing for alignment purposes tend to be quite complex. Due to their complexity, such circuits are relatively expensive. Furthermore, such circuits typically occupy large silicon area and consume a relatively large amount of power rendering it difficult to have such circuit incorporated with a transceiver in an integrated circuit. Therefore, it would be desirable to provide a method and device for implementing a built-in self-test for multi-channel transceivers which is cost effective and capable of being integrated with a transceiver in an integrated circuit.
SUMMARY OF THE INVENTION
A method and device for testing multi-channel transceivers in an integrated circuit is provided. More specifically, the present invention relates to a method and device for implementing a built-in self-test for multi-channel transceivers. The present invention includes a test pattern generator, a multiplexer, a demultiplexer, and a test result evaluator. The test pattern generator generates a test pattern which is fed into each of the input channels of the multiplexer. In an exemplary embodiment, the test pattern generator is implemented using a linear feedback shift register. The linear feedback shift register is made to cycle through its various states and its parallel output is used to form a pseudo-random test pattern. This test pattern is uniquely represented by a signature which can be used later on to determine whether the transceiver is functioning properly.
The test pattern is fed to all the input channels of the multiplexer. The multiplexer multiplexes the data from all its input channels and then relays the data to the demultiplexer. The test result evaluator then individually checks the data at each of the output channels of the demultiplexer to determine whether the data received at each output channel is the same as the test pattern.
In order to facilitate the checking process, signature analysis is utilized. The test result evaluator first records the data stream coming out of each output channel of the demultiplexer at the appropriate time. The recording is initiated when a specific bit sequence is detected. The corresponding signature for the recorded data stream is then obtained. In an exemplary embodiment, a linear feedback shift register can be used to obtain the corresponding signature. Once the corresponding signature is obtained, it is compared to the signature of the test pattern. The comparison result then indicates whether each channel of the transceiver is working properly.
Reference to the remaining portions of the specification, including the drawings and claims, will realize other features and advantages of the present invention. Further features and advantages of the present invention, as well as the structure and operation of various embodiments of the present invention, are described in detail below with respect to accompanying drawings, like reference numbers indicate identical or functionally similar elements.
REFERENCES:
patent: 3824597 (1974-07-01), Berg
patent: 5146486 (1992-09-01), Lebowitz
patent: 5412665 (1995-05-01), Gruodis et al.
patent: 5485470 (1996-01-01), Yamada
patent: 6094459 (2000-07-01), Kao et al.
Cao Jun
Momtaz Afshin
Broadcom Corporation
Chaudry Mujtaba
Christie Parker & Hale LLP
De'cady Albert
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