Built-in self-test circuit for read channel device

Details Built-in self-test circuit for read channel device Built-in self-test circuit for read channel device

1998-07-22

2000-12-19

De Cady, Albert

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

G01R 3128

Patent

active

06163865&

ABSTRACT:
A BIST circuit for use with a read channel device is disclosed that utilizes internally generated clock and control signals to control a test sequence. A linear feedback shift register is used as the signature analysis register. The test signature accumulation process is controlled by clock and control signals internal to the read charnel device that are associated with the normal operation of the read channel device.

REFERENCES:
patent: 4536706 (1985-08-01), Kemper
patent: 4543654 (1985-09-01), Jones
patent: 5533032 (1996-07-01), Johnson
patent: 5570374 (1996-10-01), Yau et al.
patent: 5574733 (1996-11-01), Kim
patent: 5640509 (1997-06-01), Balmer et al.
patent: 5680543 (1997-10-01), Bhawmik
Lee, et al., (Design, Implementation and Performance Evaluation of an MDFE Read Channel. IEEE, 1998.

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