Built-in self-test emulator

Details Built-in self-test emulator Built-in self-test emulator

2005-07-20

2010-10-19

Tabone, Jr., John J (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S028000, C714S030000, C714S736000, C711S114000, C711S128000

Reexamination Certificate

active

07818645

ABSTRACT:
Systems, methods, and a computer program are disclosed. One embodiment comprises a compiler for developing verification tests of an integrated circuit. The compiler comprises an interface and a built-in self-test (BIST) emulator. The interface includes an input and an output. The interface receives and forwards operator-level instructions to the BIST emulator, which is coupled to the output. The BIST emulator simulates the operation of a BIST module within the integrated circuit.

REFERENCES:
patent: 6351789 (2002-02-01), Green
patent: 7168005 (2007-01-01), Adams et al.
Dimitrakopoulos et al., “Virtual-Scan: A Novel Approach for Software-Based Self-Testing of Microprocessors”, May 2003, IEEE, pp. V-237-V-240.
Su et al., A computer aided engineering system for memory BIST, Jan. 30, 2001, IEEE pp. 492-495.
Chen et al., “Software-Based Self-Testing Methodology for Processor Cores”. 2001 IEEE. vol. 20. No. 3. Mar. 2001.pp. 369-380.
Wieler et al., Using an FPGA based computer as a hardware emulator for built-in self-test structures, Jun. 21, 1994, IEEE, pp. 16-21.

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