Built-in self-repair of semiconductor memory with redundant...

Details Built-in self-repair of semiconductor memory with redundant... Built-in self-repair of semiconductor memory with redundant...

2000-04-14

2003-10-28

Tu, Christine T. (Department: 2784)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S718000

Reexamination Certificate

active

06640321

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
This invention relates to semiconductor memory and, more particularly, to test and repair of semiconductor memory.
2. Description of Related Art
Semiconductor memory is a crucial resource in modem computers, being used for data storage and program execution. With the exception of the central processor itself, no other component within the computer experiences as high a level of activity. Traditional trends in memory technology are toward greater density (more memory locations, or “cells”, per part), higher speed and improved reliability. To some extent, these goals are inconsistent. For example, as memory density increases, the incidence of defects also rises. As a result, production yields of high-density memory devices with zero defects would be so low as to render them prohibitively costly. However, an alternative to building perfect devices is to build spare memory cells into the devices, along with internal circuitry capable of detecting bad cells. Additional internal circuitry swaps good cells for known-bad ones, with no degradation in performance. Therefore, as long as there are sufficiently many working cells to replace the defective ones, a fully functional memory device can be made. The techniques for internally detecting faulty memory cells and for replacing them with working cells are commonly referred to as built-in self-test (hereinafter, “BIST”) and built-in self-repair (hereinafter, “BISR”), respectively. BIST and BISR are instrumental in obtaining acceptable yields in the manufacture of high-performance semiconductor memory.
Conventional memory devices are typically organized as a matrix of rows and columns, in which each individual cell has a unique row/column address. A popular memory architecture incorporating the above-described BIST and BISR techniques configures spare memory locations as redundant rows. Thus, a nominal m×n memory device is actually configured as m rows and n columns of regular memory, and with p rows (and n columns) of redundant memory. Redundant memory rows are not part of the nominal m×n address space of the device, except when used to replace defective regular rows. Circuitry within the memory device itself performs both the test (BIST) and repair functions. During BIST, this circuitry generates test patterns to identify faulty memory locations. Then, during BISR, it reroutes internal connections, circumventing these locations and effectively replacing defective rows of regular memory with working redundant rows.
Most currently used BIST/BISR methods do not completely test the redundant rows in the memory device, but only those that are actually swapped in to replace regular memory locations that have failed. If there are enough redundant rows to replace every faulty row in the regular memory, the BIST routine certifies the memory as repairable; otherwise, it is considered non-repairable. As discussed in greater detail below, these BIST routines are not completely reliable.
A memory test generally involves writing a specific bit pattern to a range of memory cells, then reading back the values actually stored and comparing them to the desired pattern. This method can be used to locate faulty memory cells, or to detect interactions between adjacent rows, in which certain cells tend to follow the logic transitions of neighboring cells.
Typically, testing involves two BIST runs, as illustrated in FIG.
1
. During the first BIST run
10
, the regular memory is tested row by row; if a faulty row is found (i.e., one that contains a bad cell) it is replaced by the first available redundant row. The replacement row is then tested. If that row is good, testing proceeds with the next regular memory row; otherwise, the next available redundant row is swapped in and tested. This process continues until either all of the addressable memory has tested good, or there are no more redundant rows to use as replacements. In the first case, a second BIST run
12
is performed, verifying all addressable memory locations; in the second case, the memory device is flagged as non-repairable and the second BIST run
12
is skipped. Upon successful completion of the second run, the memory is certified as good. If any faulty rows are found however, the memory is classified as non-repairable. No further swapping of redundant rows for faulty rows is typically performed during second BIST run
12
.
The conventional BIST/BISR method suffers from several deficiencies. In the first place, the test routine does not test redundant memory rows until they are swapped into the addressable memory, i.e., until they are used to replace faulty rows of regular memory. This means that a test for adjacent row interaction is not done on the redundant rows before they are used as replacements. Furthermore, if row m of regular memory is found to be faulty, it is immediately replaced by a redundant row. But then row m+1 never receives a proper test for adjacent row interaction, since one of its two neighboring rows (i.e., row m) has been replaced before row m+1 is tested.
Either of the above scenarios may result in a faulty memory being certified as repairable. To make matters worse, the conventional BIST/BISR method may also flag a potentially repairable memory as bad. To understand how this can occur, consider a memory device in which regular rows
2
and
4
have shorted cells, and redundant rows
0
and
1
interact with one another. During the first BIST run, regular row
2
is replaced by redundant row
0
, which is then tested. Since redundant row
0
does not contain any shorted cells, it will test good, and the first BIST run resumes its test of regular memory with row
3
. Row
4
, being faulty, will then be replaced by redundant row
1
, followed by a simple test of redundant row
1
. Since there are presumably no shorted cells, this test will also pass. After the remainder of regular memory has been tested, the first BIST run is concluded and a second BIST run is performed on the entire addressable memory. This time, the test reveals the previously undetected interaction between redundant rows
0
and
1
, and the memory is flagged as non-repairable. But in fact, this memory could actually have been repairable, since there may have been other available redundant memory rows that could have been swapped in to replace regular rows
2
and
4
. Clearly, such false failure indications will adversely impact device production yields.
An additional drawback to the conventional BIST/BISR method is that total test time is not readily predictable. The duration of the test is dependent on the number of bad regular memory rows, each of which has to be replaced and retested. Since there is no way to know this in advance, precise test scheduling during production is impossible.
In view of the above-mentioned problems, it would be beneficial to have a more complete and robust method for self-test and self-repair of semiconductor memory devices.
SUMMARY OF THE INVENTION
The problems outlined above are in large part solved by a BIST/BISR method that completely tests both the redundant rows and the regular memory, and is capable of detecting interaction between adjacent memory rows. Only after such a complete test is performed, are redundant rows swapped for regular memory rows containing faulty cells. This ensures that potential errors resulting from interaction between rows will not be overlooked during the BIST/BISR procedure. The new method is believed to offer improved reliability over the conventional method, resulting in fewer bad memories flagged as good, and fewer good memories flagged as bad. It also has the advantage that the total test time is consistent and predictable, which benefits test scheduling.
The improved BIST/BISR routine may include three BIST runs. In an exemplary embodiment, the redundant memory rows are tested during the first run, and the regular memory rows during the second run. If the number of faulty rows of regular memory is greater than the number of available good rows of redundant me

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