Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2001-01-22
2004-02-10
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C365S201000
Reexamination Certificate
active
06691264
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
This invention relates to semiconductor memory and, more particularly, to test and repair of semiconductor memory.
2. Description of Related Art
Semiconductor memory is a crucial resource in modem computers, being used for data storage and program execution. With the exception of the central processor itself, no other component within the computer experiences as high a level of activity. Traditional trends in memory technology are toward greater density (more memory locations, or “cells,” per part), higher speed and improved reliability. To some extent, these goals are inconsistent. For example, as memory density increases, the incidence of defects also rises. As a result, production yields of high-density memory devices with zero defects would be so low as to render them prohibitively costly. However, an alternative to building perfect devices is to include spare memory cells along with the primary memory of the device. Additional internal circuitry detects faulty cells, and swaps good cells for known-bad ones. Therefore, as long as there are sufficiently many working cells to replace the defective ones, a fully functional memory device can be made. The primary memory is sometimes referred to as “accessible memory,” and the spare memory as “redundant memory.” The techniques for internally detecting faulty memory cells and for replacing them with working cells are commonly referred to as “built-in self-test” (hereinafter “BIST”) and “built-in self-repair” (hereinafter “BISR”), respectively. BIST and BISR are instrumental in obtaining acceptable yields in the manufacture of high-performance semiconductor memory.
Conventional memory devices are typically organized as a matrix of rows and columns, in which each individual cell has a unique row/column address. A popular memory architecture incorporating the above-described BIST and BISR techniques configures spare memory locations as redundant rows. Thus, a nominal m×n memory device is actually configured as m rows and n columns of accessible memory, with p rows (and n columns) of redundant memory. Redundant memory rows are not part of the nominal m×n address space of the device, except when used to replace defective accessible memory rows. Circuitry within the memory device itself performs both the test (BIST) and repair functions. During BIST, this circuitry generates test patterns to identify faulty memory locations. Then, during BISR, it reroutes internal connections, circumventing these locations and effectively replacing defective rows of accessible memory with working redundant rows.
Most currently used BIST/BISR methods test not only the accessible memory, but the redundant rows that are swapped in to replace accessible memory locations that have failed. The memory is certified as repairable only if there are enough functional redundant rows to replace every faulty row in the accessible memory; otherwise, it is considered non-repairable. A memory test generally involves writing a specific bit pattern to a range of memory cells, then reading back the values actually stored and comparing them to the desired pattern. In practice, this task is not easily accomplished. There are a variety of failure mechanisms that the BIST algorithm must be able to recognize. The simplest of these, in which memory cells are “stuck” in a particular logic state, are readily detected. Others, such as interaction between adjacent rows or columns of the memory, are less obvious. A memory cell that is susceptible to adjacent row interaction, for example, tends to follow the logic transitions of neighboring cells; this condition would not be apparent, however, if the cell were tested alone. In order to reveal interaction-related failures, memory tests are often conducted using alternating bit patterns in adjacent rows or columns of the memory matrix (commonly referred to as a “checkerboard” pattern).
It is often desirable to incorporate improvements in the BIST to achieve better fault coverage. However, in conventional BIST/BISR methods, the test and repair functions are highly interdependent. Consequently, modification of the BIST algorithm may entail corresponding changes to the BISR mechanism. Therefore, even minor changes to the test algorithm may necessitate difficult or extensive modification of the repair circuitry. In some cases, the modified BIST may be inconsistent with the existing BISR circuitry. The conventional BIST/BISR methodology is too complicated to permit upgrading BISR circuitry to support BIST enhancements.
A typical BIST/BISR method employs two BIST passes (also referred to herein as BIST “stages,” or “runs”). In the first pass, the accessible memory is tested row-by-row until a defect is encountered. The row containing the defect is then replaced by the first available redundant row and retested. This process continues until all of the accessible memory has been tested, or until there are no more redundant rows to use as replacements. In the first case, a second BIST run is performed, verifying all of the accessible memory. In the second case, the device is flagged as non-repairable. This method suffers from several drawbacks, among them the fact that the total test time is not predictable. The duration of the test is dependent on the number of bad accessible memory rows, each of which has to be replaced and retested. Since there is no way to know the test time in advance, precise test scheduling during production is impossible.
The data retention test is another critical evaluation of the memory that may be performed by the BIST. This involves writing a test pattern to the memory, waiting for some prescribed interval, and then reading the memory to determine whether the test pattern was retained. The conventional BIST/BISR method is so complicated that it can significantly prolong data retention tests and make the results difficult to evaluate.
In view of the above-mentioned problems, it would be desirable to have a method for built-in self-repair of semiconductor memory devices in which the BISR mechanism is substantially independent of the BIST mechanism, such that changes to the BIST could be accommodated with little or no modification to the BISR. Ideally, the BISR could be integrated with any BIST engine without modification. Under the method, the BISR should be consistent with upgrading fault coverage capability in the BIST, e.g., readily supporting improved versions of tests for adjacent row interaction, data retention, etc. In addition, a system embodying the method should be efficient and permit estimation of total test time.
SUMMARY OF THE INVENTION
The problems outlined above are addressed by a system and method for a self-repairing memory that can be integrated with any BIST mechanism, without extensive modification to either the BIST or BISR mechanisms. A BISR “Wrapper” system interfaces the BIST engine to the BISR repair circuitry. The BISR Wrapper makes use of standard status signals present in any BIST engine, and directs the operation of the BISR circuitry. With the Wrapper, BISR operation need no longer be closely coupled to the operation or internal structure of the BIST. Consequently, modification of the BIST mechanism, e.g., to improve fault coverage, can be implemented without influencing the BISR. This is believed to be an important advantage of the new method, since a major impediment to BIST enhancement is often the collateral effort involved in redesigning the BISR. The new method also has the advantage that test time is consistent and predictable.
The system disclosed herein may be used for self-test and self-repair of a memory comprising first and second arrays. In an embodiment, the system consists of a first m×n memory array, a second p×n memory array, a single built-in self-test (BIST) engine adapted to test the first and second arrays as a single joint array and detect rows failing the test, and repair circuitry. The BIST is configured to generate row addresses that span the entire memory array (i.e., m+n rows). Acc
Abraham Esaw
Conley Rose & Tayon
LSI Logic Corporation
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