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CMOS circuits including a passive element having a low end...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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CMOS compatible process for making a charge trapping device

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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CMOS compatible process with different-voltage devices

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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CMOS device

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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CMOS device and fabricating method thereof

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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CMOS device and method for fabricating the same

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
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CMOS device and method of manufacturing the same

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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CMOS device fabrication method with PMOS interface...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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CMOS device structure with reduced risk of salicide bridging and

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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CMOS device structure with reduced short channel effect and memo

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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CMOS device structures and method of making same

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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CMOS device with deep current path for ESD protection

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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CMOS device with dual-epi channels and self-aligned contacts

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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CMOS device with metal and silicide gate electrodes and a...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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CMOS device with raised source and drain regions

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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CMOS devices having dual high-mobility channels

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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CMOS devices with a single work function gate electrode and...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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CMOS devices with balanced drive currents based on SiGe

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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CMOS devices with different metals in gate electrodes using...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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CMOS devices with hybrid channel orientations and method for...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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