CMOS device fabrication method with PMOS interface...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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Details

C438S287000, C438S591000, C257SE21194

Reexamination Certificate

active

08076193

ABSTRACT:
According to one aspect of the invention, there is provided a semiconductor device fabrication method comprising:forming a first gate electrode via a first gate insulating film on a P-type semiconductor region formed in a surface portion of a semiconductor substrate, and forming a second gate electrode via a second gate insulating film on an N-type semiconductor region formed in the surface portion of the semiconductor substrate;forming a first insulating film on side surfaces of the first gate electrode and the first gate insulating film, and forming a second insulating film on side surfaces of the second gate electrode and the second gate insulating film;forming a mask having a pattern corresponding to the P-type semiconductor region;etching away the second insulating film by using the mask;removing the mask; andforming a first gate electrode sidewall insulating film on the side surfaces of the first insulating film, and forming a second gate electrode sidewall insulating film on the side surfaces of the second gate electrode and the second gate insulating film, thereby forming an interface insulating film in an interface between the second gate electrode and the second gate insulating film.

REFERENCES:
patent: 09-205151 (1997-08-01), None
patent: 2000-216373 (2000-08-01), None
patent: 2004-289061 (2004-10-01), None
patent: 2005-108875 (2005-04-01), None
Watanabe et al., “Impact of Hf Concentration on Performance and Reliability for HfSiON-CMOSFET”, IEDM Tech. Dig., IEEE, pp. 20.3.1-20.3.4, (2004).
Notification of Reasons for Rejection issued by the Japanese Patent Office on Aug. 5, 2011, for Japanese Patent Application No. 2005-281537 and English language translation thereof.

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