LandOfFree - US Patents - Listing for Semiconductor device manufacturing: process,Making field effect device having pair of active regions...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Sacrificial nitride and gate replacement

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer

Sacrificial oxide for minimizing box undercut in damascene...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Sacrificial polysilicon sidewall process and rapid thermal...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Sacrificial polysilicon sidewall process and rapid thermal...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Sacrificial self aligned spacer layer ion implant mask...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Sacrificial silicon sidewall for damascene gate formation

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Sacrificial spacer layer method for fabricating field effect...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Salicide device with borderless contact

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Salicide field effect transistors with improved borderless...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Salicide formation on narrow poly lines by pulling back of space

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Salicide integration method

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Salicide integration process for embedded DRAM devices

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Salicide process

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Salicided gate for virtual ground arrays

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Salicided gate for virtual ground arrays

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Salicided gate for virtual ground arrays

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Save MOS device

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Scalable EPROM array

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Scalable Flash/NV structures and devices with extended...