CMOS device structure with reduced risk of salicide bridging and

Details CMOS device structure with reduced risk of salicide bridging and CMOS device structure with reduced risk of salicide bridging and

1996-07-17

1997-09-16

Trinh, Michael

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438217, 438231, 438233, 438664, 438683, H01L 218238

Patent

active

056680244

ABSTRACT:
A method for forming a CMOS device, with improved yield, performance and reliability characteristics, has been developed. Yield improvements have been addressed by the use of a dual insulator spacer, used to reduce the risk of salicide bridging, as well as the use of pocket implantation regions, used to reduce punchthrough leakage. An ultra shallow junction extension region has been created in a peripheral channel region, reducing the resistance of this region, thus enhancing the performance of the CMOS device. In addition, ultra lightly doped source and drain regions are used to relax reliability concerns, regarding hot electron injection.

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