CMOS device structures and method of making same

Details CMOS device structures and method of making same CMOS device structures and method of making same

2000-11-21

2001-10-16

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S301000, C438S302000, C438S303000, C438S305000, C438S306000, C438S307000, C438S308000

Reexamination Certificate

active

06303450

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to improved CMOS devices.
BACKGROUND OF THE INVENTION
The manufacture of complementary metal oxide semiconductors (CMOSs), such as metal oxide semiconductor field effect transistors (MOSFETs) is well known in the art. However, as the envelope of the technology is pushed to higher performance and the size of the transistors scaled down, three major problems have been identified, namely canyon effects, facet effects of selective epitaxy, and lateral redistribution of dopants.
Canyon effects appear in stacked MOSFET configurations, such as in a series of NFETs, for example, without source or drain metal contacts. In such cases the amount of doping for deep source and drain is affected by the distance between adjacent gates (i.e., the gate-to-gate pitch). As gate-to-gate pitch decreases, so does the deep source/drain (S/D) doping. When source/drain dopants are implanted through the smaller opening between the adjacent gates, the less amount of dopant is introduced into the S/D region, which tends to diffuse outwardly and significantly reduce the peak concentration of dopant. In forming the S/D doping in silicon-on-insulator (SOI) substrates, the less-doped S/D regions in a smaller gate-to-gate pitch causes serious problems such as incomplete junction isolation between the adjacent devices due to incomplete butting of S/D doping against the SOI buried oxide interface, as a function of the gate-to-gate pitch. The result is current leakage between adjacent devices and degraded performance and irregularity in circuit operation with such devices.
Facet effects occur as the result of building up raised source/drain (RSD) structures in an effort to avoid silicide contact formation problem in SOI devices and potentially reduce S/D resistance. The RSD structure is desired for higher performance characteristics. At present, there is poor control over the facet that is formed at the gate sidewall because of the difference in epitaxy growth rates as a function of crystal orientation and spacer geometry. Faceting of the crystal is a thermodynamic artifact of the minimization of free energy. Various facets are formed at the silicon dioxide (SiO
2
) gate sidewall depending on sidewall orientation and growth conditions, particularly during epitaxy of silicon or silicon germanium (SiGe). The uncontrollable variation in facet shapes and contours interferes with critical doping by implantation, usually necessitating application of extension and halo doping prior to epitaxy of the RSD. The result is degraded short channel behavior because the extension and halo dopants exhibit transient enhanced diffusion (TED) during the thermal process of selective epi.
Lateral redistribution of extension and halo dopants results in aggravated short channel effects, particularly when scaling the gate length to under 0.1 micron. The most obvious short channel effect is threshold voltage (Vt) rolloff. A number of theoretical studies indicate that Vt rolloff can only be improved by providing a sharper lateral gradient of halo doping, which would require the reduction or elimination of TED of halo dopant during activation annealing of deep submicron scale devices. This is particularly a problem with boron or indium for NFET halo, which is known to diffuse out significantly from S/D sides at gate lengths as short as 0.1 microns.
This invention is a method of making CMOS structures at deep submicron scale that exhibit substantially reduced canyon effects, facet effects, and lateral dopant diffusion.
SUMMARY OF THE INVENTION
Disclosed is a method comprising providing a silicon surface with an underlying insulator layer, providing a plurality of gates adjacent to source/drain regions, growing source/drains between said gates such that said source/drains are thicker in regions of larger gate-to-gate pitch, and doping said source/drains with one or more dopants such that said dopants abut said underlying insulator layer.


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