Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
1999-02-12
2001-03-20
Pham, Long (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S163000, C438S164000, C257S351000
Reexamination Certificate
active
06204100
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is related to a semiconductor device, and more particularly, to a CMOS(Complementary Metal Oxide Semiconductor) device and a method for fabricating the same which has improved operation speed and reliability.
2. Discussion of the Related Art
There have been ceaseless efforts in fabrication of a semiconductor integrated circuit for reducing a size of an MOSFET(Metal Oxide Semiconductor Field Effect Transistor) which can provide a highly integrated high performance semiconductor chip. The size has been scaled down to a sub-micron level. The size reduction of the semiconductor device should be both in horizontal and vertical directions for balancing with various device characteristics. That is, in the device size reduction, for example, if a distance between a source and a drain comes closer in a transistor, undesirable changes in the characteristics of device occur, e.g., the short channel effect. In order to improve the short channel effects in a high density device, an LDD(Lightly Doped Drain) structure is employed, in which low concentration junctions are formed under sidewalls of a gate.
FIG. 1
illustrates an equivalent circuit for a background art CMOS invertor.
In general, as shown in
FIG. 1
, the background art CMOS invertor is provided with an NMOS transistor Q
1
and a PMOS transistor Q
2
. The NMOS transistor Q
1
and PMOS transistor Q
2
are connected in series, with their gates receiving an input signal Vin in common. A drain of the NMOS transistor Q
1
is connected to a ground terminal Vss, a source of the PMOS transistor Q
2
is adapted to be supplied with a static voltage Vdd, and connection terminals of the NMOS transistor Q
1
and the PMOS transistor Q
2
are provided as an output terminal Vout.
A background art CMOS device and a method for fabricating the same will be explained with reference to the attached drawings.
FIG. 2
illustrates a section of the background art CMOS device.
Referring to
FIG. 2
, the background art CMOS transistor is provided with an n-well
12
and a p-well
13
formed in surfaces of the semiconductor substrate
11
, field oxide films
14
formed in isolating region and field regions of the n-well
12
and the p-well
13
, first and second gate electrodes
16
a
and
16
b
formed on the gate insulating film
15
in active regions of the n-well
12
and the p-well
13
isolated by the field oxide film
14
, insulating film sidewalls
22
at both sides of the first and second gate electrodes
16
a
and
16
b
respectively, and heavily doped p type impurity regions
24
and heavily doped n type impurity regions
26
, both with LDD structures, in surfaces of the semiconductor substrate
11
on both sides of the first and second gate electrodes
16
a
and
16
b
respectively.
FIGS. 3A
to
3
I illustrate sections showing the steps of a background art method for fabricating a CMCS device.
Referring to
FIG. 3A
, n type impurity ions and p type impurity ions are selective injected into predetermined regions of a semiconductor substrate
11
and subjected to drive in diffusion, to form an n-well
12
and a p-well
13
in surfaces of the semiconductor substrate
11
. Then, an initial oxide film and a nitride film are formed in succession on an entire surface of the semiconductor substrate
11
, subjected to photolithography and etching to remove the nitride film selectively to define field regions and active regions, and an LOCOS(local oxidation of silicon) is conducted to form field oxide films
14
on an interface region of the n-well
12
and the p-well
13
and field regions.
As shown in
FIG. 3B
, a gate insulating film
15
and a gate electrode polysilicon layer
16
are formed on an entire surface of the semiconductor substrate
11
inclusive of the field oxide films
14
. Then, a first photoresist film
17
is formed on the polysilicon layer
16
and subjected to exposure and development for patterning the first photoresist film
17
. As shown in
FIG. 3C
, the polysilicon layer
16
and the gate insulating film
15
are selectively removed using the patterned photoresist film
17
as a mask, to form first and second gate electrodes
16
a
and
16
b
in active regions on the n-well
12
and the p-well
13
.
As shown in
FIG. 3D
, the first photoresist film
17
is removed, and a second photoresist film
18
is coated on an entire surface of the semiconductor substrate
11
inclusive of the first, and second gate electrodes
16
a
and
16
b
and subjected to patterning by exposure and development, to leave the second photoresist film
1
only over the p-well
13
region. Then, p type impurities are lightly injected into an entire surface of the semiconductor substrate
11
using the patterned second photoresist film
18
as a mask, to form first LDD(Lightly Doped Drain) regions
19
in surfaces of the semiconductor substrate
11
on both sides of the first gate electrode
16
a.
As shown in
FIG. 3E
, the second photoresist film
18
is removed, and a third photoresist film
20
is coated on an entire surface of the semiconductor substrate
11
inclusive of the first, and second gate electrodes
16
a
and
16
b
and subjected to patterning by exposure and development, to leave the third photoresist film
20
only over the n-well region
12
. Then, n type impurities are injected into an entire surface of the semiconductor substrate
11
using the patterned third photoresist film
20
as a mask, to form second LDD regions
21
in surfaces of the semiconductor substrate
11
on both sides of the second gate electrode
16
b.
As shown in
FIG. 3F
, the third photoresist film
20
is removed, and an insulating film is formed on an entire surface or the semiconductor substrate
11
inclusive of the first, and second gate electrodes
16
a
and
16
b
and is etched back, to form insulating film sidewalls
22
at both sides of the first, and second gate electrodes
16
a
and
16
b.
As shown in
FIG. 3G
, a fourth photoresist film
23
is coated on an entire surface of the semiconductor substrate
11
inclusive of the first and second gate electrodes
16
a
and
16
b
and subjected to patterning by exposure and development to leave the fourth photoresist film
23
only over the n-well region. Then, source/drain p type impurities are heavily injected into an entire surface of the semiconductor substrate using the patterned fourth photoresist film
23
as a mask, to form heavily doped p type impurity regions
24
connected to the first LDD regions
19
in surfaces of the semiconductor substrate
11
on both sides of the first gate electrode
16
a
. The first gate electrode
16
a
and the heavily doped p type impurity regions
24
form a PMOS device.
As shown in
FIG. 3H
, the fourth photoresist film
23
is removed, and a fifth photoresist film
25
is coated on an entire surface of the semiconductor substrate
11
inclusive of the first and second gate electrodes
16
a
and
16
b
and subjected to patterning by exposure and development, to leave the fifth photoresist film
25
only over the p-well region
21
. Then, source/drain n type impurities are heavily injected into an entire surface of the semiconductor substrate
11
using the patterned fifth photoresist film
25
as a mask, to form heavily doped n type impurity regions
26
connected to the second LDD regions
21
in surfaces of the semiconductor substrate
11
on both sides of the second gate electrode
16
b
. The second gate electrode
16
b
and the heavily doped impurity regions
26
on both sides thereof form an NMOS device.
As shown in
FIG. 3I
, by removing the fifth photoresist film
25
, fabrication of a CMOS device formed with an NMOS device and a PMOS device or. an n-well
12
and a p-well
13
in a semiconductor substrate
11
respectively is completed.
However, the background art CMOS device and a method for fabricating the CMOS device have the following problems.
First, the hot carrier effect caused by Junction capacitances between the source/drain regions increases as device size is scaled down t
Hyundai Electronics Industries Co,. Ltd.
Pham Long
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