[DRAM structure and fabricating method thereof]
2F-square memory cell for gigabit memory applications
3-D CMOS transistors with high ESD reliability
3-D CMOS-on-SOI ESD structure and method
4 F2 folded bit line DRAM cell structure having buried bit...
4F-square memory cell having vertical floating-gate transistors
8 bit per cell non-volatile semiconductor memory structure...
Abrupt junction formation by atomic layer epitaxy of in situ...
Abrupt source/drain extensions for CMOS transistors
Absorber layer candidates and techniques for application
Absorber layer for DSA processing
Absorber layer for DSA processing
Activating source and drain junctions and extensions using a...
Active matrix backplane for controlling controlled elements...
Active matrix device with photo sensor
Active matrix ESD protection and testing scheme
Active matrix organic light emitting display and method of...
Active matrix organic light emitting display and method of...
Active matrix pixel device construction method
Active matrix substrate and liquid crystal display device,...