CMOS device structure with reduced short channel effect and memo

Details CMOS device structure with reduced short channel effect and memo CMOS device structure with reduced short channel effect and memo

1997-12-12

2000-02-01

Fahmy, Wael

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438302, 438305, 257408, H01L 218238, H01L 21336

Patent

active

060202289

ABSTRACT:
The method of manufacturing a semiconductor integrated circuit device, which has an n-channel MIS transistor and a p-channel MIS transistor formed in the same semiconductor substrate, comprises ion implantation processes using the same photoresist as masks. The ion implantation processes include a step of injecting an impurity ion into the semiconductor substrate 1 to form the source and drain of an n-channel MOSFET 3n, a p type semiconductor region 4p for suppressing the short channel effect, and an n-well power supply region 10n, and a step of injecting an impurity ion into the semiconductor substrate 1 to form the source and drain of a p-channel MOSFET 3p, an n type semiconductor region 4n for suppressing the short channel effect, and a p-well power supply region 10p.

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patent: 5413945 (1995-05-01), Chien et al.
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patent: 5757045 (1998-05-01), Tasi et al.
patent: 5759901 (1998-06-01), Loh et al.
patent: 5796145 (1998-08-01), Sato

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