CMOS device

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C438S199000, C438S787000, C438S791000

Reexamination Certificate

active

07022561

ABSTRACT:
A method comprising providing a substrate having an NMOS device adjacent a PMOS device and forming a first stress layer over the NMOS and PMOS devices, wherein the first stress layer comprises a first tensile-stress layer or a compression-stress layer. An etch stop layer is formed over the first stress layer, and portions of the first stress layer and the etch stop layer are removed from over the NMOS device, leaving the first stress layer and the etch stop layer over the PMOS device. A second tensile-stress layer is formed over the NMOS device and over the first stress layer and the etch stop layer, and portions of the second tensile-stress layer and the etch stop layer are removed from over the PMOS device, leaving the second tensile-stress layer over the NMOS device.

REFERENCES:
patent: 5562770 (1996-10-01), Chen et al.
patent: 5834363 (1998-11-01), Masanori
patent: 6271054 (2001-08-01), Ballantine et al.
patent: 6281532 (2001-08-01), Doyle et al.
patent: 6284610 (2001-09-01), Cha et al.
patent: 6403482 (2002-06-01), Rovedo et al.
patent: 6444566 (2002-09-01), Tsai et al.
patent: 6573172 (2003-06-01), En et al.
patent: 6599792 (2003-07-01), Jung
patent: 6678307 (2004-01-01), Ezaki et al.
patent: 6737308 (2004-05-01), Kim
patent: 2002/0058186 (2002-05-01), Nozawa et al.
patent: 2002/0175146 (2002-11-01), Dokumaci et al.
patent: 2004/0099910 (2004-05-01), Choe et al.
patent: 2004/0110377 (2004-06-01), Cho et al.
J. Welser et al.,Strain Dependence of the Performance Enhancement in Strained-Si n-MOSFETs,IEDM Tech, Dig., pp. 373-376, 1994.
K. Rim et al.,Strained Si NMOSFET's for High Performance CMOS Technology,VLSI Tech., pp. 59 and 60, 2001.
F. Ootsuka et al.,A Highly Dense, High-Performance 130nm node CMOS Technology for Large Scale System-on-a-Chip Applications,IEDM Tech. Dig., pp. 575-578, 2000 article.
Shinya Ito et al.,Mechanical Stress Effect of Etch-Stop Nitride and its Impact on Deep Submicron Transistor Design,IEDM Tech., Dig. pp. 247-250, 2000 article.
A. Shimizu et al.,Local Mechanical—Stress Control (LMC): A New Technique for CMOS—Performance Enhancement,IEDM Tech. Dig., pp. 433-436, 2001 article.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

CMOS device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with CMOS device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and CMOS device will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3612953

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.