P-channel dynamic flash memory cells with ultrathin tunnel...
Packing density for flash memories
Pad stack with a poly SI etch stop for TEOS mask removal with RI
Pair of FETs including a shared SOI body contact and the...
Parallel and series-coupled transistors having gate...
Parasitic surface transfer transistor cell (PASTT cell) for...
Partial recrystallization of source/drain region before...
Partial silicidation method to form shallow source/drain junctio
Partial silicide gate in sac (self-aligned contact) process
Partial vertical memory cell and method of fabricating the same
Partially depleted SOI field effect transistor having a...
Passivated silicon carbide devices with low leakage current...
Passivated tiered gate structure transistor and fabrication...
Passivation of nitride spacer
Passivation of wide band-gap based semiconductor devices...
Passivation scheme for LCD and other applications
Passivation structure for flash memory and method for...
Pattern density control using edge printing processes
Pattern density control using edge printing processes
Pattern formation method and method of manufacturing display...