Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2011-08-30
2011-08-30
Loke, Steven (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S299000, C438S231000, C438S478000
Reexamination Certificate
active
08008157
ABSTRACT:
A method of forming a semiconductor structure includes forming a PMOS device and an NMOS device. The step of forming the PMOS device includes forming a first gate stack on a semiconductor substrate; forming a first offset spacer on a sidewall of the first gate stack; forming a stressor in the semiconductor substrate using the first offset spacer as a mask; and epitaxially growing a first raised source/drain extension (LDD) region on the stressor. The step of forming the NMOS device includes forming a second gate stack on the semiconductor substrate; forming a second offset spacer on a sidewall of the second gate stack; epitaxially growing a second raised LDD region on the semiconductor substrate using the second offset spacer as a mask; and forming a deep source/drain region adjoining the second raised LDD region.
REFERENCES:
patent: 5504031 (1996-04-01), Hsu et al.
patent: 5834343 (1998-11-01), Ogasawara et al.
patent: 6235568 (2001-05-01), Murthy et al.
patent: 6479358 (2002-11-01), Yu
patent: 6562686 (2003-05-01), Lee
patent: 6790733 (2004-09-01), Natzle et al.
patent: 7037818 (2006-05-01), Dokumaci et al.
patent: 7078742 (2006-07-01), Lin et al.
patent: 7098514 (2006-08-01), Oh et al.
patent: 7112495 (2006-09-01), Ko et al.
patent: 7164163 (2007-01-01), Chen et al.
patent: 7348248 (2008-03-01), Cheng
patent: 7358551 (2008-04-01), Chidambarrao et al.
patent: 7361563 (2008-04-01), Shin et al.
patent: 2005/0112817 (2005-05-01), Cheng et al.
patent: 2005/0170594 (2005-08-01), Yeo et al.
patent: 2005/0184345 (2005-08-01), Lin et al.
patent: 2006/0003533 (2006-01-01), Kammler et al.
patent: 2006/0088968 (2006-04-01), Shin et al.
patent: 2006/0131656 (2006-06-01), Shin et al.
patent: 2007/0020864 (2007-01-01), Chong et al.
patent: 2007/0138570 (2007-06-01), Chong et al.
patent: 2007/0194387 (2007-08-01), Dyer et al.
patent: 2008/0277735 (2008-11-01), Ko et al.
patent: 2009/0068810 (2009-03-01), Tsai et al.
patent: 253716 (2006-04-01), None
Adey, J., et al., “Enhanced Dopant Solubility in Strained Silicon,” Journal of Physics: Condensed Matter, vol. 16 (2004) pp. 9117-9126, IOP Publishing Ltd., UK.
Wakabayashi, H., et al., “Improved Sub-10-nm CMOS Devices with Elevated Source/Drain Extensions by Tunneling Si-Selective-Epitaxial-Growth,” Electron Devices Meeting, 2005, IEDM Technical Digest, IEEE International, Dec. 2005, pp. 145-148.
Yasutake, N., et al., “A hp22 nm Node Low Operating Power (LOP) Technology with Sub-10 nm Gate Length Planar Bulk CMOS Devices,” 2004 Symposium on VLSI Technology Digest of Technical Papers, IEEE, pp. 84-85.
Hokazono, A., et al., “Source/Drain Engineering for Sub-100 nm CMOS Using Selective Epitaxial Growth Technique,” IEEE 2000, IEDM 00-243, pp. 10.6.1-10.6.4.
Thompson, S.E., et al., “A 09-nm Logic Technology Featuring Strained-Silicon,” IEEE Transactions on Electron Devices, vol. 51, No. 11, Nov. 2004, pp. 1790-1797.
Chen Hung-Ming
Huang Chien-Chao
Liang Chun-Sheng
Yang Fu-Liang
Goodwin David
Loke Steven
Slater & Matsil L.L.P.
Taiwan Semiconductor Manufacturing Company , Ltd.
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