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Integrated circuit devices with high and low voltage...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Integrated circuit devices with high and low voltage...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
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Integrated circuit employing simultaneously formed isolation and

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Integrated circuit fabrication

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Integrated circuit fabrication

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Integrated circuit fabrication method with buried oxide isolatio

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
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Integrated circuit gate conductor having a gate dielectric which

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Integrated circuit gate conductor which uses layered spacers...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Integrated circuit having a jet vapor deposition silicon nitride

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Integrated circuit having a memory cell transistor with a...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Integrated circuit having at least two vertical MOS...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Integrated circuit having at least two vertical MOS...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Integrated circuit having increased gate coupling capacitance

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Integrated circuit having independently formed array and...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Integrated circuit having multiple LDD and/or source/drain impla

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Integrated circuit having sacrificial spacers for producing...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Integrated circuit having temporary conductive path...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Integrated circuit having ultralow-K dielectric layer

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Integrated circuit including a first gate stack and a second...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Integrated circuit including a graded grain structure for enhanc

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
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