Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-01-24
2004-07-13
Fahmy, Jr., Wael (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S279000, C438S283000, C438S523000, C438S587000
Reexamination Certificate
active
06762084
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and particularly relates to a dynamic random access memory (which will be referred to as a “DRAM” hereinafter).
2. Description of the Background Art
In recent years, demands for semiconductor memory devices have been rapidly increased owing to rapid and wide spread of information equipments such as computers. Regarding a function, devices having a large-scale storage capacity and a high operation speed have been demanded. In view of this, technical development has been made for improving a density, a responsibility and a reliability of semiconductor memory devices.
The DRAM is a kind of semiconductor memory device allowing random input/output of storage information. The DRAM is generally formed of a memory cell array, which is a storage region storing large storage information, and a peripheral circuitry required for external input and output.
FIGS. 37A and 37B
show a DRAM having conventional memory cells of a stacked type. Referring to
FIGS. 37A and 37B
, a p-type semiconductor substrate
1
is provided at its main surface with a p-type impurity region
3
. A field insulating film
2
and p-type impurity regions
4
a
and
4
b
are formed on p-type impurity region
3
. p-type impurity regions
4
a
and
4
b
are provided for controlling threshold voltages of transistors.
Lightly doped n-type impurity regions
5
which are spaced from each other are formed at the surface of p-type impurity region
4
a
. Lightly doped n-type impurity regions
5
and heavily doped n-type impurity regions
7
are formed at spaced portions of the surface of p-type impurity region
4
b.
Gate electrodes
12
are formed on the main surface of semiconductor substrate
1
in the memory cell portion with gate insulating films
8
b
therebetween, respectively, and gate electrodes
12
are also formed on the main surface of semiconductor substrate
1
in the peripheral circuitry with gate insulating films
9
therebetween, respectively. Gate insulating films
8
and
9
are equal in thickness. Each gate electrode
12
is formed of a polycrystalline silicon film
10
and a WSi film
11
.
A TEOS (Tetra Btyle Ortho Silicate) is formed on gate electrode
12
, and a side wall insulating film
14
is formed on the side wall of gate electrode
12
. Gate electrodes
12
are covered with an interlayer insulating film
15
extending through the memory cell portion and the peripheral circuitry. Contact holes
15
a
and
15
b
are formed in interlayer insulating film
15
.
A bit line
16
a
having a portion located within contact hole
15
a
extends on interlayer insulating film
15
, and an interconnection layer
16
b
having a portion located within contact hole
15
b
extends on interlayer insulating film
15
. Bit line
16
a
and interconnection layer
16
b
are covered with an interlayer insulating film
17
. Contact holes
17
a
which reach lightly doped n-type impurity regions
5
, respectively, extend through interlayer insulating films
17
and
15
.
Storage nodes
18
which have portions located within contact holes
17
a
, respectively, extend on interlayer insulating film
17
. A surface of each storage node
18
is covered with a capacitor insulating film
19
, over which a cell plate
20
is formed. Cell plate
20
, capacitor insulating film
19
and storage node
18
form a capacitor
21
.
Capacitors
21
and interlayer insulating film
17
are covered with an interlayer insulating film
22
. The peripheral circuitry is provided with a contact hole
23
a
extending through interlayer insulating films
22
and
17
, a contact hole
23
b
reaching corresponding gate electrode
12
and a contact hole
23
c
reaching heavily doped n-type impurity region
7
. Metal interconnections
24
b
,
24
c
and
24
d
, which have portions located within contact holes
23
a
,
23
b
and
23
c
, respectively, extend on interlayer insulating film
22
. In the memory cell portion, metal interconnections
24
a
are formed on interlayer insulating film
22
.
In recent years, elements have been further miniaturized, and the thicknesses of gate insulating films
8
b
and
9
have been reduced. Particularly, a concentration of p-type impurity region
4
a
for controlling a threshold voltage of the transistor in the memory cell portion have been increased in accordance with the above reduction in thickness. Consequently, such a problem is becoming manifest that a leak current at a pn-junction (which will be merely referred to as a “junction leak current” hereinafter) increases.
According to the isolating structure of the trench type shown in
FIGS. 37A and 37B
, there is a tendency that a stress concentrates at the vicinity such as a region A and B of the periphery of field insulating film
2
. In this case, the junction leak current cannot be suppressed sufficiently because the source/drain of the transistor in the memory cell portion are formed of only lightly doped n-type impurity region
5
. Further, an etching damage is liable to occur at region A when side wall insulating film
14
is etched. This also becomes a cause of generation of the junction leak current. Such a junction leak current may destroy data stored in storage node
18
.
Further, the foregoing increase in concentration of p-type impurity region
4
a
for the threshold voltage control causes disadvantageous increase in sheet resistance of lightly doped n-type impurity region
5
.
SUMMARY OF THE INVENTION
The invention has been developed to overcome the above problems. An object of the invention is to reduce a junction leak current.
According to an aspect, a semiconductor device of the invention includes a first transistor having a gate insulating film of a first thickness, and a second transistor having a gate insulating film of a second thickness smaller than the first thickness. At least one of source/drain of the first transistor is formed of a first lightly doped region and a first heavily doped region. At least one of source/drain of the second transistor includes a second lightly doped region and a second heavily doped region higher in concentration than the first heavily doped region.
As described above, the gate insulating film of the first transistor is thicker than the gate insulating film of the second transistor so that it is possible to lower a concentration of an impurity region provided for controlling a threshold voltage of the first transistor. Thereby, it is possible to lower a junction leak current. Since at least one of source/drain of the first transistor has the first heavily doped region, the junction leak current can be lower than that in the prior art even if a field insulating film is adjacent to the source/drain. Further, provision of the forgoing first heavily doped region can reduce the sheet resistance of the source/drain. Since the second transistor has the second heavily doped region of a higher concentration than the first heavily doped region, the sheet resistance of the source/drain can be sufficiently reduced.
At least one of the source/drain of the second transistor may have a medium-doped region having a concentration higher than the second lightly doped region and lower than the second heavily doped region.
By providing the medium-doped region as described above, it is possible to surround the second heavily doped region by the medium-doped region. Thereby, it is possible to avoid direct contact of the second heavily doped region with an impurity region of a different conductivity type so that concentration of an electric field can be suppressed. This also contributes to reduction in junction leak current.
Preferably, the semiconductor device includes a memory cell portion for storing data and a peripheral circuit portion for external input/output. In this case, it is preferable that the memory cell portion includes the first transistor, and the peripheral circuit portion includes the second transistor.
The above structure in which the memory cell includes the first tra
Arima Hideaki
Shimizu Masahiro
Tanaka Yoshinori
Fahmy Jr. Wael
McDermott & Will & Emery
Peralta Ginette
Renesas Technology Corp.
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