Integrated circuit having ultralow-K dielectric layer

Details Integrated circuit having ultralow-K dielectric layer Integrated circuit having ultralow-K dielectric layer

2006-12-22

2010-11-09

Smith, Zandra (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S378000

Reexamination Certificate

active

07829422

ABSTRACT:
A device layer is configured to reduce change in stress characteristics due to subsequent processing to reduce cracking of a subsequently formed layer. The change in stress characteristics can be reduced by providing a shield layer over the device layer to protect the device layer from exposure to subsequently processing, such as curing medium used to form voids in an ultralow-k dielectric layer.

REFERENCES:
patent: 2008/0124855 (2008-05-01), Widodo et al.
patent: 02065534 (2002-08-01), None
patent: 03095702 (2003-11-01), None

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