Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1998-03-11
2000-08-22
Wojciechowicz, Edward
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438231, 438305, 438525, 438527, 257335, 257408, H01L 2972
Patent
active
061071293
ABSTRACT:
An integrated circuit is formed whereby MOS transistor junctions are produced which enhance the overall speed of the integrated circuit. The transistor junctions include multiple implants into the lightly doped drain (LDD) areas of the junction, the source/drain areas of the junction or both the LDD and source/drain areas. The first implant of the multiple implants serves to condition the implant area so that the second and subsequent implants are accurately placed with relatively high concentrations closely below the substrate surface. The resulting junction is therefore one which has relatively high drive strength, low contact resitivity, low source-to-drain parasitic resistance, and relatively low junction capacitance.
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patent: 5516711 (1996-05-01), Wang
patent: 5567965 (1996-10-01), Kim
patent: 5591650 (1997-01-01), Hsu et al.
patent: 5793090 (1998-08-01), Gardner et al.
Fulford Jr. H. Jim
Gardner Mark I.
Hause Fred N.
Advanced Micro Devices , Inc.
Daffer Kevin L.
Wojciechowicz Edward
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