Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-10-07
2001-02-27
Wilczewski, Mary (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S593000, C438S294000
Reexamination Certificate
active
06194267
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates generally to the field of electronic devices, and more particularly, to an integrated circuit having independently formed array and peripheral isolation dielectrics.
BACKGROUND OF THE INVENTION
One type of modern nonvolatile memory is the EPROM or EEPROM device that uses floating gate structures. These floating gate memory structures may be integrated into a floating gate array which facilitates interface between the memory cells, control circuitry and high-voltage power sources. The memory cells use channel hot electrons for programming from the drain side and use Fowler-Nordheim tunneling for erasure from the source side. Due to the high voltages frequently used to program and erase the cells, high-voltage peripheral transistors may be implemented to provide an interface between a high-voltage source and the memory cells of the floating gate array. The control logic circuitry of the floating gate array typically functions with a lower operating voltage. Low-voltage peripheral transistors may be implemented to provide the logic circuitry for the array.
It is often desirable to fabricate peripheral transistors and the floating gate memory cells on a common semiconductor substrate. To ensure that each cell operates independently, regions of isolation dielectric may be formed between cells to electrically isolate the gates from one another. Typically, the isolation dielectrics for the memory cells are formed at the same time and are of the same construction as the isolation dielectrics for the peripheral transistors. In addition, to ensure appropriate coupling coefficients, the distal ends of floating gates in the memory cell area are made to overlap the isolation dielectric. The proper voltage applied to the control gate is proportional to the coupling coefficient of the device. Providing overlap of the ends of the floating gates over the isolation dielectric increases the coupling coefficient, allowing for a lower control gate voltage.
This approach has several disadvantages. One problem with this approach is that it is difficult to instill unique characteristics into the separate isolation dielectrics because they are formed contemporaneously. For example, memory cells frequently use high voltages for programming and erasing data. Peripheral transistors interfacing high voltage sources typically implement thicker gate oxides and larger isolation dielectric regions than those typically associated with memory cell gate oxides. Additionally, as memory cell sizes are reduced, their corresponding gate oxides become thinner and isolation dielectric regions become smaller. An approach that contemporaneously forms isolation dielectrics for memory cells and peripheral transistors cannot satisfy theses diverging specifications.
Another problem with this approach is that as the memory cells are scaled, they become intolerant to low levels of leakage current. The read current of each memory cell is directly proportional to the area of substrate supporting the floating gate, and inversely proportional to the thickness of the oxide separating the substrate and the floating gate. To facilitate integration with other scaled system elements, the width of the floating gates is frequently decreased. Maintaining a desired overlap of the floating gate over the isolation dielectric, however, requires a corresponding decrease in the substrate area supporting the gate. Decreasing this area width without reducing the gate oxide thickness results in degradation of the cell's read current. To maintain a desired read current, therefore, the thickness of the gate oxide must also decrease. Unfortunately, it is often impractical to decrease the gate oxide thickness because this leads to high levels of stress-induced leakage current. Therefore, it is difficult to scale these devices without either degrading the cell's read current or making them susceptible to stress-induced leakage currents.
Another problem with this approach is that the overlapping regions result in complex device topography, making it difficult to etch all of the polysilicon from the areas between floating gates. Failure to remove all of the polysilicon between floating gates may cause adjacent floating gates to short out.
Still another problem with this approach is that when used in conjunction with a configuration comprising trenches and moats within the substrate, the gate oxide layer tends to thin around the trench corners, causing data retention and threshold voltage nonuniformities.
SUMMARY OF THE INVENTION
In accordance with the teachings of the present invention, an integrated circuit having independently formed array and peripheral isolation dielectrics is provided that substantially eliminates or reduces the disadvantages associated with the prior techniques and processes.
According to one embodiment of the present invention, a method of forming an integrated circuit comprises forming a first dielectric layer disposed outwardly from a semiconductor substrate and forming a first intermediate structure outwardly from the first dielectric layer. The first intermediate structure comprises a floating gate layer disposed outwardly from the first dielectric layer, a second dielectric layer disposed outwardly from the floating gate layer and a first polysilicon layer disposed outwardly from the second dielectric layer. Next, regions of the first intermediate structure are removed to form at least one gate stack disposed outwardly from the substrate. After the formation of the gate stacks, at least one dielectric isolation region is formed between two gate stacks.
The invention has several important technical advantages. The dielectric isolation regions of the array are formed independently of the peripheral dielectric regions. Peripheral dielectric regions may be formed to a desired thickness for high voltage devices, while array dielectric regions may be scaled to minimize cell size. Additionally, the invention eliminates overlap between the distal ends of the floating gates and the isolation dielectric residing between the gates. The area of substrate supporting each floating gate may be maintained or increased despite the scaling of the floating gate width. A good read current is, therefore, maintained without creating stress-induced leakage current by thinning the gate oxide layer. Eliminating overlap between the floating gates and the isolation dielectric also facilitates creation of floating gates with little or no topography, making it easier to remove all polysilicon from between the floating gates. Use of relatively flat polysilicon layers solves problems associated with floating gate shorts caused by residual polysilicon residing between the floating gates. Also, because the floating gates do not extend beyond the trench corners, problems associated with oxide thinning such as nonuniformities in data retention and threshold voltages are reduced or eliminated.
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Brady III Wade James
Garner Jacqueline J.
Goodwin David
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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