Integrated circuit gate conductor which uses layered spacers...

Details Integrated circuit gate conductor which uses layered spacers... Integrated circuit gate conductor which uses layered spacers...

1998-09-16

2001-07-10

Chaudhuri, Olik (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S229000, C438S230000, C438S231000, C438S232000, C438S301000, C438S303000, C438S306000, C257S336000, C257S408000

Reexamination Certificate

active

06258680

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor processing and, more particularly, to a method of forming layers of sidewall spacers upon a gate conductor to produce a graded junction which minimizes hot-carrier effects.
2. Description of the Relevant Art
Fabrication of a metal-oxide-semiconductor (“MOS”) transistor is well-known. Fabrication begins by lightly doping a single crystal silicon substrate n-type or p-type. The specific area where the transistor will be formed is then isolated from other areas on the substrate using various isolation structures. In modem fabrication technologies, the isolation structures may comprise shallow trenches in the substrate filled with dielectric oxide which acts as an insulator. Isolation structures may alternatively comprise, for example, locally oxidized silicon (“LOCOS”) structures. A gate dielectric is then formed by oxidizing the silicon substrate. Oxidation is generally performed in a thermal oxidation furnace or, alternatively, in a rapid-thermal-anneal (“RTA”) apparatus. A gate conductor is then patterned from a layer of polycrystalline silicon (“polysilicon”) deposited upon the gate dielectric. The polysilicon is rendered conductive by doping it with ions from an implanter or a diffusion furnace. The gate conductor is patterned using a mask followed by exposure, development, and etching. Subsequently, source and drain regions are doped, via ion implantation, with a high dosage n-type or p-type dopant. If the source and drain regions are doped n-type, the transistor is referred to as NMOS, and if the source and drain regions are doped p-type, the transistor is referred to as PMOS. A channel region between the source and the drain is protected from the implant species by the pre-existing gate conductor. When voltage above a certain threshold is applied to the gate of an enhancement-mode transistor, the channel between the source and drain becomes conductive and the transistor turns on.
FIG. 1
shows a top view of such a transistor. The transistor is formed in active region
26
of semiconductor substrate
10
, between isolation areas
18
and
20
. Isolation areas
18
and
20
preferably comprise shallow trench isolation structures filled with a dielectric oxide. A polysilicon layer is deposited upon the semiconductor topography and then patterned to form gate conductor
22
. N-type or p-type species are implanted into the semiconductor substrate to form source region
26
, drain region
28
, and to render the polysilicon layer conductive. An interlevel dielectric is then deposited upon the semiconductor topography (not shown) to electrically isolate the underlying transistor from the overlying metal layers. Contact holes are etched into the interlevel dielectric and then metal is deposited into the holes to establish electrical contacts. Structures
42
,
44
, and
46
are such electrical contacts. Electrical contact
42
is described in more detail in subsequent cross-sectional views along plane A.
FIG. 2
is a partial cross-sectional view along plane A of semiconductor substrate
10
. Isolation structure
18
is shown as a shallow trench isolation structure. Gate conductor
22
is shown terminating over and above isolation structure
18
. Conformal oxide layer
30
is then deposited upon the semiconductor topography preferably using a CVD process. Oxide layer
30
is then etched using an anisotropic plasma etch. An anisotropic etch removes the oxide from substantially horizontal surfaces faster than oxide from substantially vertical surfaces. The anisotropic etch thereby leaves spacers
32
and
34
on the vertical sidewall surfaces of gate conductor
22
. Spacer structures
32
and
34
are typically formed for two reasons: (i) to be used in forming a lightly doped drain (“LDD”) structure, and (ii) to be used in aligning silicide areas on the source, drain, and gate conductor.
FIG. 3
is a processing step subsequent to
FIG. 2
in which an interlevel dielectric
36
is deposited across the semiconductor topography. Interlevel dielectric
36
is deposited to electrically isolate the underlying gate conductors and source and drain regions from the subsequently formed, overlying metal interconnect. Interlevel dielectric
36
typically comprises glass deposited using a spin-on process or chemical vapor deposition. Boron and phosphorus may be incorporated into the glass during the deposition to reduce stress in the glass, improve step coverage, and to enable the dielectric to flow at lower temperatures. After initial deposition, the upper surface of interlevel dielectric
36
follows the contour of the underlying structure. The wafer is then heated, typically at a temperature of approximately 800° C., and interlevel dielectric
36
flows to fill in existing gaps and produce a more planar upper surface.
FIG. 4
is a processing step subsequent to
FIG. 3
in which a photoresist layer is deposited upon interlevel dielectric
36
and then patterned to expose portion
38
of the upper surface of interlevel dielectric
36
. A hole is subsequently etched through interlevel dielectric
36
. An anisotropic etch is typically used which combines physical and chemical etching. This produces a hole with substantially vertical sidewalls. The chemical part of the etch is selected so as to be selective to oxide. Since spacer
34
comprises silicon dioxide, it is also attacked by the etchant and may also be removed during the etch process. In that case, the etchant will reach the trench dielectric fill which also typically comprises some form of oxide. As a result, since all these materials have very similar responsiveness to the etch, the etch may go completely through the isolation material fl
8
to silicon substrate
10
. Etches are usually stopped by the presence of a material with dissimilar etch characteristics. When such a material is detected, a signal is sent and the etch stops. In this case, since all the materials present have similar etch characteristics, it is difficult at best to determine etch end point. The result shown in
FIG. 4
indicates removal of an oxide spacer; however, a spacer of dissimilar material (i.e., nitride or polysilicon) would not be removed.
FIG. 5
is a processing step subsequent to
FIG. 4
in which a metal
44
is deposited into contact
42
opening for the establishment of an electrical connection. Metals like aluminum or tungsten are typically used. Chemical-mechanical polishing (“CMP”) is applied to the wafer to remove any metal exterior to the hole and planarize the top surface. After the CMP, upper surface of metal
44
is at the same vertical level as upper surface of interlevel dielectric
36
. Metal
44
is deposited to electrically connect the gate conductor to the source and both of them to an overlying metal interconnect line. The gate conductor is shorted to the source so that the transistor emulates a diode. If the previous etch has attacked the trench dielectric so that a hole exists into the underlying silicon, an undesirable electrical short will also be established between semiconductor substrate
10
, gate conductor
22
and the source of the transistor. It would therefore be desirable to prevent the etchant from attacking the underlying trench dielectric. This will prevent metal from being deposited upon the exposed substrate silicon and establishing an electrical short.
Spacers
32
and
34
serve to reduce the maximum electric field E
m
which exists near the drain side of the channel area. Although not shown in
FIGS. 2-5
, the channel area exists along plane B of FIG.
1
. The spacers occur not only in the active regions but also on all sidewall surfaces associated with the gate conductors. Absent spacers, an inversion-layer charges (or carriers) are accelerated into the overlying gate oxide. The carriers become trapped in the gate dielectric, a phenomenon generally called the hot-carrier effect. The injection of hot carriers into the gate dielectric damages the substrate/gate dielectric interface. Over time, operational characteristics of

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