Integrated circuit including a graded grain structure for enhanc

Details Integrated circuit including a graded grain structure for enhanc Integrated circuit including a graded grain structure for enhanc

1997-08-01

1999-03-30

Niebling, John F.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

438154, 438200, H01L 2100, H01L 2184, H01L2008238

Patent

active

058888535

ABSTRACT:
An elevated transistor formation includes a plurality of planes upon which transistors are formed. The plurality of transistor planes are formed at multiple relative elevations overlying a substrate wafer using deposited polysilicon to form a substrate between the layers. The polysilicon is deposited in a multiple-grain form to achieve an advantageous balance between deposition rate and substrate quality. In particular, columnar polysilicon is deposited at a temperature of approximately 620.degree. C. and above to achieve a high deposition rate directly overlying a lower-elevation transistor plane. High quality polysilicon is then deposited overlying the columnar polysilicon layer at a temperature of approximately 580.degree. C. or below. The deposition rate for high quality polysilicon is substantially lower than the deposition rate for columnar polysilicon. The highest quality substrate, upon which transistors in an elevated transistor plane are formed, is amorphous polysilicon.

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