Integrated circuit employing simultaneously formed isolation and

Details Integrated circuit employing simultaneously formed isolation and Integrated circuit employing simultaneously formed isolation and

1996-10-08

1998-06-09

Dang, Trung

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438259, 438296, 438430, 438589, H01L 21336

Patent

active

057633100

ABSTRACT:
A semiconductor fabrication process in which a transistor trench and an isolation trench are simultaneously formed in a semiconductor substrate. The transistor trench is laterally displaced from the isolation trench. Thereafter the isolation trench is filled with an isolation material and a gate dielectric is formed on the floor of the transistor trench. Next, a conductive gate is formed on the gate dielectric and a source/drain impurity distribution is introduced into a source region and a drain region of the semiconductor substrate. The drain region and the source region are laterally disposed on either side of the transistor trench. In a presently preferred embodiment, the semiconductor substrate comprises a substantially single crystal p+ silicon bulk and a p- epitaxial layer formed upon the p+ silicon bulk. Preferably, the process of forming a transistor trench and the isolation trench includes depositing a photoresist layer on an upper surface of the semiconductor substrate, patterning the photoresist layer to expose an upper surface of an isolation trench region and an upper surface of a transistor trench region, anisotropically etching the isolation trench and the transistor trench region with a chlorinated plasma and stripping the photoresist layer. The process of filling the isolation trench with an isolation material preferably comprises depositing an isolation dielectric on the topography defined by the upper surface of the semiconductor substrate and the isolation trench and removing the isolation dielectric from regions exterior to the isolation trench.

REFERENCES:
patent: 4536782 (1985-08-01), Brown
patent: 4830975 (1989-05-01), Bovaird et al.
patent: 5093273 (1992-03-01), Okumura

Affiliated with

Also associated with

Rating

Integrated circuit employing simultaneously formed isolation and does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Integrated circuit employing simultaneously formed isolation and, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit employing simultaneously formed isolation and will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2198435