Integrated circuit having increased gate coupling capacitance

Details Integrated circuit having increased gate coupling capacitance Integrated circuit having increased gate coupling capacitance

2000-02-15

2004-01-27

Zarabian, Amir (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S424000

Reexamination Certificate

active

06682978

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to an integrated circuit having increased gate coupling capacitance. The present invention further relates to an integrated circuit having a conductive layer optimized for gate coupling capacitance.
BACKGROUND OF THE INVENTION
The present invention applies particularly to the fabrication of nonvolatile memory integrated circuits (e.g., flash, EPROM, EEPROM, etc.), but may find applications in other integrated circuits. Nonvolatile memory integrated circuits are used in a wide variety of commercial and military electronic devices, including hand held telephones, radios and digital cameras. The market for these electronic devices continues to demand lower voltage, lower power consumption and decreased chip size. Also, the demand for greater functionality is driving the design rule lower, from the 0.35-0.25 micron technology of today to 0.18 micron, 0.15 micron and lower.
A conventional flash memory cell of a flash memory IC is illustrated in
FIGS. 1 and 2
.
FIG. 1
depicts a cross-sectional view along the bit line direction of a single flash memory cell
10
on a substrate
11
. Cell
10
includes a first transistor
12
and a second transistor
14
. Each of transistors
12
,
14
includes a tunnel oxide layer
16
, a first polysilicon layer
18
,
20
, an interpoly dielectric layer
22
,
24
, a second polysilicon layer
26
,
28
, a silicide layer
30
,
32
and sidewall spacers
34
,
36
.
With reference first to
FIGS. 2-7
, a conventional flash memory cell fabrication process is illustrated. A substrate
11
is shown in
FIGS. 2-7
in a cross-sectional view along the word line direction. Substrate
11
includes a shallow trench isolation structure (STI)
40
between devices (not shown), such as, metal-oxide-semiconductor field effect transistors (MOSFETs), memory cells, or other devices. STI
40
includes an oxide fill material
42
. A tunnel oxide layer
16
is provided above substrate
11
. First and second polysilicon wings
46
,
48
are patterned in first polysilicon layer
20
. Interpoly dielectric layer
24
is provided above polysilicon wings
46
,
48
and also above STI
40
. Second polysilicon layer
28
and silicide layer
32
are provided above interpoly dielectric layer
24
.
Referring now to
FIG. 3
, STI
40
is formed by first applying a pad oxide layer
50
over substrate
11
and subsequently growing or depositing a nitride layer
52
. A STI mask and etch step forms STI recess
54
. Referring now to
FIG. 4
, an STI liner oxide
56
is provided to line recess
54
followed by a trench fill with a PECVD oxide fill material
58
(Plasma Enhanced Chemical Vapor Deposition). As shown in
FIG. 5
, a planarization step and a trench CMP (Chemical Mechanical Polishing) step are applied to PECVD oxide fill material
58
to remove the oxide above nitride layer
52
and partially along sides
60
,
62
of nitride layer
52
.
Referring now to
FIG. 6
, a nitride strip step removes nitride layer
52
. Pad oxide layer
50
is removed by sacrificial oxidation. Subsequently, a tunnel oxide layer
64
is grown above substrate
11
. Referring now to
FIG. 7
, a first polysilicon layer
20
is applied. Layer
20
is patterned (i.e., masked and etched) to form wings
46
,
48
. Referring again to
FIG. 2
, interpoly dielectric layer
24
(e.g., Oxide Nitride Oxide) is grown over wings
46
,
48
. Second polysilicon layer
28
is then deposited, followed by deposition of silicide layer
32
.
In operation, a data element is stored on polysilicon layers
18
,
20
(FIG.
1
), also called the floating gate. Access to the data element is obtained via second polysilicon layers
26
,
28
, also called the control gate or wordline. While the voltage of the data element is typically on the order of 3.3 Volts, the voltage that must be applied to the control gate to access this data element is on the order of 9 Volts. Thus, a charge pump (not shown) is located on the flash memory IC to raise the chip voltage from 3.3 Volts to a target voltage of 9 Volts.
Charge pumps are large, taking up substantial space on the flash memory cell and further comprising the reliability of the IC. As design rules continue to decrease, the size of the charge pump becomes an obstacle in chip design. However, the size of the charge pump can be decreased by decreasing the target voltage. The target voltage can be decreased by increasing the gate coupling ratio (a) of the memory cell. Gate coupling ratio (&agr;) is defined as:
&agr;=
C
ono
/(
C
ono
+C
tox
)
where C
ono
is the capacitance between first polysilicon layer
18
,
20
and second polysilicon layer
26
,
28
and C
tox
is the capacitance between substrate
11
and first polysilicon layer
18
,
20
.
Accordingly, what is needed is an IC and method of fabricating an IC to increase the gate coupling ratio, decreasing the target voltage of the charge pump, thereby decreasing power consumption of the IC, decreasing the size of the charge pump, and improving reliability.
SUMMARY OF THE INVENTION
These and other limitations of the prior art are addressed by the present invention which is directed to an integrated circuit having an increased gate coupling capacitance. The integrated circuit includes a substrate having a surface, the substrate having a trench extending below the surface. A trench fill material is disposed in the trench and has a portion extending above the surface. A first conductive layer is adjacent the trench fill material and has a portion extending over the portion of the insulative material. An insulative layer is adjacent the first conductive layer and a second conductive layer is adjacent the insulative layer.
According to another embodiment of the present invention, a method of fabricating an integrated circuit on a substrate is provided. The method includes forming a trench in the substrate, the trench extending below a surface of the substrate, providing a trench fill material in the trench such that the trench fill material extends above the surface of the substrate, and providing a first conductive layer over at least a portion of the trench fill material.
According to yet another embodiment of the present invention, integrated circuit having an increased gate coupling capacitance is disclosed. The integrated circuit is fabricated by a process including forming a trench in the substrate, the trench extending below a surface of the substrate; providing a trench fill material in the trench such that the trench fill material extends above the surface of the substrate; and providing a first conductive layer over at least a portion of the trench fill material.


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