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Mosfet with raised source and drain regions

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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MOSFET with reduced leakage current

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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MOSFET with self-aligned channel edge implant and method

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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MOSFET with self-aligned silicidation and gate-side air-gap stru

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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MOSFET with short channel structure and formation method...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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MOSFET-fused nonvolatile read-only memory cell (MOFROM)

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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MOSFETs comprising source/drain regions with slanted upper...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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MOSFETS with a recessed self-aligned silicide contact and an ext

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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MOSFETs with improved short channel effects and method of...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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MSM binary switch memory

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Multi-bit memory unit and fabrication method thereof

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Multi-bit non-volatile integrated circuit memory and method...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Multi-bit non-volatile memory device and method therefor

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Multi-bit stacked-type non-volatile memory and manufacture...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Multi-component strain-inducing semiconductor regions

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Multi-depth junction formation tailored to silicide formation

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Multi-gate semiconductor device and method for forming the same

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Multi-layer reducible sidewall process

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Multi-layer silicide block process

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Multi-layer silicon nitride deposition method for forming low ox

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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