Multi-bit non-volatile integrated circuit memory and method...

Details Multi-bit non-volatile integrated circuit memory and method... Multi-bit non-volatile integrated circuit memory and method...

2005-09-06

2005-09-06

Le, Thao P. (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257S315000, C257S316000, C438S257000

Reexamination Certificate

active

06939767

ABSTRACT:
A non-volatile memory (10) includes at least two buried bit lines (45, 47) formed within a semiconductor substrate (12), a charge storage layer (18) overlying the semiconductor substrate (12); a control gate (26) overlying the charge storage layer (18); an insulating liner (30) overlying the control gate; and first and second conductive sidewall spacer control gates (32, 34). Multiple programmable charge storage regions (42) and (41, 44) are created within the charge storage layer (18) beneath respective ones of the control gate (26) and the first and second sidewall spacer control gates (32, 34). Also, the non-volatile memory (10) is a virtual ground NOR type multi-bit flash EEPROM (electrically erasable programmable read only memory). By using conductive sidewall spacers as the control gates, a very dense multi-bit non-volatile memory can be manufactured.

REFERENCES:
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patent: 5969383 (1999-10-01), Chang
patent: 6091102 (2000-07-01), Sekariapuram et al.
patent: 6201282 (2001-03-01), Eitan
patent: 6630384 (2003-10-01), Sun et al.
patent: 6635533 (2003-10-01), Chang et al.
Eitan et al., “NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell,” IEEE Electron Device Letters, vol. 21, No. 11, Nov. 2000, pp. 543-545.
Chang et al., “New SONOS Memory Using Source-Side Injection for Programming,” IEEE Electron Device Letters, vol. 19, No. 7, Jul. 1998, pp. 253-255.

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