MOSFET with self-aligned silicidation and gate-side air-gap stru

Details MOSFET with self-aligned silicidation and gate-side air-gap stru MOSFET with self-aligned silicidation and gate-side air-gap stru

1997-10-17

1999-06-22

Trinh, Michael

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438305, 438595, 438563, H01L 21336

Patent

active

059151820

ABSTRACT:
The method of the present invention includes forming a silicon dioxide layer. A polysilicon layer is then deposited on the silicon dioxide layer. Next, a gate structure is formed by etching. A silicon oxynitride layer is formed on the substrate and covers the gate structure. Silicon nitride side-wall spacers are formed on the side walls of the gate. An amorphous silicon layer is formed on the substrate, the side-wall spacers, and top of the polysilicon gate. Then, the source and the drain are formed. A wet oxidation is subsequently carried out to convert the amorphous silicon into a doped oxide layer. An etching process is then utilized to etch the oxide layer. Therefore, oxide side-wall spacers are formed on the silicon nitride side-wall spacers. Then, a metal silicide layer is formed on top of the gate, and on the source and the drain. The silicon nitride side-wall spacers are removed to form air gaps between the gate and the side-wall spacers. Then, a low energy pocket ion implantation is performed to doped ions into the substrate via the air gaps. Next, an oxide is formed on the substrate, spacers and over the gate. Then, a rapid thermal process (RTP) is carried out for annealing.

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Togo et al, "A Gate-Side Air-gap Structure (GAS) to reduce the Parasitic Capacitance in MOSFETs", 1996 Symposium on VLSI Tech. Digest of Technical Papers, pp. 38-39.
Ruth DeJule, "Meeting the Ultra-Shallow Junction Challenge", Apr. 1997, Semiconductor International 50-54, 56.

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