Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-05-06
2002-04-30
Potter, Roy (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S154000, C438S232000, C438S289000, C438S532000
Reexamination Certificate
active
06380015
ABSTRACT:
This invention relates to improved complementary metal oxide semiconductor (MOS) field effect transistors (FET). More particularly, this invention relates to improved low power, low threshold voltage MOSFETs and a method of making them.
BACKGROUND OF THE INVENTION
Alternating p-type and n-type MOSFETs are used to make complementary metal oxide semiconductor (CMOS) devices for memory and logic applications such as DRAMS and microprocessors. P-type MOS devices require boron channel implants which transform the PFET to a buried channel device. Such devices are more prone to short channel effects, such as a lowering of the threshold voltage, than surface channel devices, as is known. As semiconductor devices become smaller, and as the industry moves to very large scale integrated circuits (VLSI), which use 1 micron design rules, and even ultra large scale integrated circuits (ULSI) that use 0.5 micron design rules, these short channel effects become more marked because the channel implant dosage must be increased. Further, n+ gate p-type FETs have gate-induced drain leakage problems due to larger workfunction differences, which will increase as channel lengths become shorter and gate oxide thickness is reduced. At some point this limits the use of p-type buried channel FETs for CMOS processing.
Various investigators have tried to reduce these problems. Very shallow channel ion implants and shallow source/drain junctions have been tried to improve the short channel characteristics, but the increased technical difficulties of performing these shallow ion implants and the low post-ion implant processing temperatures imposed on such devices have added to the costs of making them. In any case as a practical matter this approach cannot be used for gate lengths below about 0.5 micron.
Thus, other workers have addressed the problem of trying to increase threshold voltage. Lowering the compensating channel implant dose is one way to increase the threshold voltage, but this approach is limited to a maximum threshold voltage of 1 volt for a supply voltage V
DD
=5V, and it cannot be used at all for 0.5 micron CMOS technologies that will use reduced voltages V
DD
=3V. Further, none of the above proposals reduce gate induced drain leakage or reduce the gate oxide fields, which are related to the gate work function difference.
The use of a surface channel p-type FET has also been proposed to overcome the limitations of buried channel p-type FETs, using a boron-doped p-type gate instead of an n-type gate. CMOS requires of course making both p
+
gates and n
+
gates. However, a very high boron concentration, about 1×10
20
/cm
3
, is required to achieve doped p
+
gates, which can lead to boron penetration into the gate oxide. This in turn leads to oxide degeneration, gate depletion effects and to threshold voltage shifts caused by lateral dopant diffusion within the n
+
or p
+
gate stacks unless very low temperatures are maintained during processing. Further, exposure of highly doped p
+
gates to even small amounts of hydrogen or fluorine cannot be tolerated, but the presence of these elements is difficult to eliminate or control because they are present in silicon oxide and silicon nitride layers.
Thus the search for a method of improving the short channel characteristics of sub-micron buried channel PFETs has continued.
SUMMARY OF THE INVENTION
According to the present invention, improved short channel effects are obtained in buried channel FETs by modifying the gate workfunction difference. In accordance with the invention, the n
+
gate for a p-type MOSFET is partially counter-doped with boron to produce a modified p-type FET. The p-type FET of the invention has improved short channel effects, reduced threshold voltage, reduced gate induced drain leakage and reduced gate oxide fields which improve the reliability of these devices. In effect, the gate workfunction difference is adjusted with the boron, but without changing the essentially n-type characteristics of the gate.
In accordance with the method of the invention, counter-doped polycide gate layers are made by depositing a pre-doped n
+
polysilicon layer over a silicon or silicon oxide substrate, depositing a thin sacrificial layer of silicon oxide or silicon nitride thereover, ion implanting boron to change the workfunction of the gate, and removing the sacrificial layer prior to completing formation of the gate.
REFERENCES:
patent: 4555842 (1985-12-01), Levinstein et al.
patent: 4808555 (1989-02-01), Mauntel et al.
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