MOSFET with self-aligned channel edge implant and method

Details MOSFET with self-aligned channel edge implant and method MOSFET with self-aligned channel edge implant and method

2000-06-29

2002-10-29

Chaudhuri, Olik (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257S510000, C438S296000, C438S391000

Reexamination Certificate

active

06472274

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor chip devices and manufacturing methods and, particularly, to a metal-oxide-semiconductor-field-effect-transistor (MOSFET)device and method. The method involves forming a MOSFET device by,selectively doping bordering channel regions such that, in operation, the threshold, or turn-on, voltage is equalized across the channel. The device structure comprises a self-aligned channel edge implant region for equalizing threshold voltages in the channel edge region with threshold voltages in the channel interior region, thereby reducing sub-threshold leakage current in low voltage applications.
2. Discussion of the Prior Art
A schematic diagram of a typical MOSFET device is shown in FIG.
1
. As shown in
FIG. 1
, the MOSFET comprises a wafer of silicon (a semiconductor)
1
having two highly doped regions of opposite polarity diffused therein to form a source
2
and a drain
3
region.
Disposed on the semiconductor
1
, between the source
2
and the drain
3
regions, is an insulative gate
4
comprising, for example, silicon dioxide (a dielectric). Disposed on top of the gate dielectric is a metal contact
5
.
In operation, when a voltage (refered to as a gate voltage) is applied to the gate metal
5
with respect to the drain or source terminal (not shown), a “field effect” is triggered in the semiconductor
1
under the gate and between the source
2
and the drain
3
such that either a build-up or a depletion of charge occurs in the semiconductor
1
under the gate. Whichever event occurs depends on the doping conductivity type of the semiconductor
1
under the gate, and the polarity of the gate voltage. Particularly, the build-up or depletion of charges in the semiconductor
1
creates under the gate
4
, a channel
6
that electrically connects the source
2
and drain
3
. In this condition, the surface of the semiconductor
1
is said to be inverted, and a current will flow in the channel in response to the-gate voltage, i.e., an increase in the gate voltage will increase the size of the channel and increase the channel current; alternatively, an decrease in the gate voltage will decrease the channel current. By controlling the gate voltage, the device can function as a switch or an amplifier.
In MOSFET devices, for current to flow along the channel, a minimum gate voltage must be applied. This minimum voltage is called the threshold voltage, and it is an important parameter in the operation of the MOSFET device.
Also in MOSFET devices, due to variations in the gate dielectric thickness over the channel, and variations in the charge density and interface charge trapping density across the channel, the threshold at the channel edges is typically lower compared to the threshold voltage at the corresponding inner region of the channel.
A consequence of the lower threshold voltage at the channel edge is that current conduction along the edges will occur at a different, typically lower, gate voltage (V
G
) than in the inner region. This is depicted schematically in
FIG. 3
wherein current conduction at the channel edge (I
e
) is shown to occur at lower gate voltages than (I
c
) in the interior of channel.
The edge current, which contributes to what is known as the “off-state leakage” or sub-threshold voltage leakage current”, is undesirable particularly for applications that require a low “off-state” leakage current; these applications require a MOSFET which exhibits very low leakage current in its “off-state”, for example in low power applications to conserve power, or in DRAM applications to prevent data loss through charge leakage.
The problem of sub-threshold leakage current has been recognized and several prior art solutions have been claimed; see, for example, U.S. Pat. No. 5,994,202A, U.S. Pat. No. 5,643,822 and U.S. Pat. No. 5,798,533. Notwithstanding the prior art, however, the problem persists to varying degrees, hence the need for improvement in this area.
Accordingly, it is desirable to form a MOSFET device structure wherein the sub-threshold leakage current is eliminated or at least minimized. That is, it is desirable to form a MOSFET device structure wherein, application of a gate voltage, the threshold voltage in the channel is such that the threshold edge voltage and the threshold voltage in the interior of the channel are equal or substantially equalized. In other words, it is desirable to form a MOSFET device that exhibits sharp turn-on characteristics.
SUMMARY OF THE INVENTION
In view of the deficiencies in the prior MOSFET devices, it is an object of the present invention to provide a MOSFET device structure having self-aligned channel edge implant region for exhibiting significantly reduced or eliminated sub-threshold leakage current in low voltage applications.
It is also an objective of the invention to provide a method of manufacturing MOSFET device having self-aligned channel edge implant region for exhibiting significantly reduced or eliminated sub-threshold current leakage in low voltage applications.
These and other objectives are accomplished by a MOSFET device and manufacturing method where the device is formed by selectively doping the channel edge region, the method comprising the steps of:
a) depositing a masking layer over a planar surface of a silicon substrate;
b) patterning and etching through said masking layer into said silicon substrate to form first and second trenches defining a MOSFET device active area;
c) selectively etching back said masking material to expose regions of un-etched silicon at border regions of said MOSFET device active area, said border regions defining MOSFET device channel edges;
d) selectively doping said exposed border regions to form drain and source portions each including a respective MOSFET channel edge;
e) filling said trench with an electrically insulating material and removing remaining masking layer;
f) forming a MOSFET gate on and in unetched areas of said MOSFET device active area, wherein a said MOSFET device exhibits reduced or eliminated threshold leakage current in low-voltage applications.
Thus, by the method, a self-aligned mask is formed over the MOSFET device active area including the channel region, laterally etching the mask over the channel region to expose a thin, precisely defined border of underlaying silicon at the edge of the MOSFET device channel, and selectively doping the exposed region. Thereafter, the masking is removed and the MOSFET device is formed in between the exposed channel region. Because the masking process is self-aligned process, the definition of the channel edge and formation of the doping mask can be performed with a single photolithograph step.
The MOSFET device fabricated in accordance with the method of the invention, comprises:
a semiconductor substrate, said substrate comprising a doped source region and a doped drain region, said source and drain regions separated by a channel region and each respectively comprising a doped channel edge region;
a gate disposed on said substrate between said source and drain region substantially covering said channel region, wherein the respective channel edge regions is selectively doped such that when applying a voltage to said gate, a voltage is established in said channel region such that the voltage in said channel edge region is substantially equal to the voltage in a channel interior region.


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