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[DRAM structure and fabricating method thereof]

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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2F-square memory cell for gigabit memory applications

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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3-D CMOS transistors with high ESD reliability

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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4 F2 folded bit line DRAM cell structure having buried bit...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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4F-square memory cell having vertical floating-gate transistors

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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8 bit per cell non-volatile semiconductor memory structure...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Abrupt junction formation by atomic layer epitaxy of in situ...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Abrupt source/drain extensions for CMOS transistors

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Absorber layer candidates and techniques for application

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Absorber layer for DSA processing

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Absorber layer for DSA processing

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Activating source and drain junctions and extensions using a...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Active region implant methodology using indium to enhance...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Adaptive negative differential resistance device

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Adaptively controlled, self-aligned, short channel device and me

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Adding a poly-strip on isolation's edge to improve...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Additional buffer layer for eliminating ozone/tetraethylorthosil

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Additional post-glass-removal processes for enhanced cell...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Adhesive material for programmable device

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Adjustable threshold isolation transistor

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