[DRAM structure and fabricating method thereof]
2F-square memory cell for gigabit memory applications
3-D CMOS transistors with high ESD reliability
4 F2 folded bit line DRAM cell structure having buried bit...
4F-square memory cell having vertical floating-gate transistors
8 bit per cell non-volatile semiconductor memory structure...
Abrupt junction formation by atomic layer epitaxy of in situ...
Abrupt source/drain extensions for CMOS transistors
Absorber layer candidates and techniques for application
Absorber layer for DSA processing
Absorber layer for DSA processing
Activating source and drain junctions and extensions using a...
Active region implant methodology using indium to enhance...
Adaptive negative differential resistance device
Adaptively controlled, self-aligned, short channel device and me
Adding a poly-strip on isolation's edge to improve...
Additional buffer layer for eliminating ozone/tetraethylorthosil
Additional post-glass-removal processes for enhanced cell...
Adhesive material for programmable device
Adjustable threshold isolation transistor