P-channel dynamic flash memory cells with ultrathin tunnel...

Packing density for flash memories

Pad stack with a poly SI etch stop for TEOS mask removal with RI

Parallel and series-coupled transistors having gate...

Parasitic surface transfer transistor cell (PASTT cell) for...

Partial recrystallization of source/drain region before...

Partial silicidation method to form shallow source/drain junctio

Partial silicide gate in sac (self-aligned contact) process

Partial vertical memory cell and method of fabricating the same

Passivated silicon carbide devices with low leakage current...

Passivation of nitride spacer

Passivation of wide band-gap based semiconductor devices...

Pattern density control using edge printing processes

Pattern density control using edge printing processes

Patterned backside stress engineering for transistor...

Patterned backside stress engineering for transistor...

Patterning methodology for uniformity control

Patterning of doped poly-silicon gates

Patterning SOI with silicon mask to create box at different...

PECVD silicon-rich oxide layer for reduced UV charging