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Test pattern generating method and test pattern generating syste

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Test pattern generation

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Test pattern generation apparatus and method for SDRAM

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Test pattern generation circuit and method for use with...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Test pattern generation method for avoiding false testing in...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Test pattern generator

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Test pattern generator and test pattern generation

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Test pattern generator for memories having a block write functio

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Test pattern generator for SRAM and DRAM

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Test pattern generator having improved test sequence compaction

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Test pattern generator, a memory testing device, and a...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Test pattern generator, a testing device, and a method of...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Test pattern generator, propagation path disconnecting...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Test patterns to insure read signal integrity for high speed...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Test patterns to insure read signal integrity for high speed...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Test permutator

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Test pin gating for dynamic optimization

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate

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Test program debugger device, semiconductor test apparatus,...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Test program generation system and test program generation...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Test program set generation tool

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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